[sdiy] Delays: how?

[j vallier]

My solution uses a Xilinx Spartan FPGA, Crystal CS4216 codec, and a SRAM. 
Works Great although I currrently have to change patameters in VHDL and 
recompile a bitstream when I want to change...

The latest add-on which I have simulated but not tested in HW uses a cheapo 
8-bit ADC as a "CV" input. The CV obviously goes into the ADC analogue 
input. The 8-bit ADC output can be routed to 3 internal registers selected 
by DIP switches (in the breadboarded version) to modify one of 4 parameters 
in real-time:

- SRAM address LSB (fine delay time)
- SRAM address MSB (coarse delay time)
- LFO rate
- LFO depth

I'm working on my DIY website where I'll post details.

regards,

Peff



>From: Ingo Debus <debus at cityweb.de>
>To: synth-diy at dropmix.xs4all.nl
>Subject: Re: [sdiy] Delays: how?
>Date: Thu, 26 Dec 2002 14:46:57 +0100
>
>Magnus Danielson wrote:
>>The question then comes if one should vary the sample-rate or if one
>>should change the offset between the read and write counters in the
>>memory.
>
>Varying the sample rate would require a fast ADC to get a decent delay time 
>range (high sample rate for short delay).
>
>I think varying the address offset (between read and write address) to 
>modulate the delay time isn't that bad. There are single samples repeated 
>or skipped when the delay time gets longer/shorter. If the modulation 
>source is, say, a ramp, it becomes effectively a staircase. If this is 
>still to "steppy", just increase the sample rate to make the stair steps 
>finer. Memory chips are cheap.
>
>There were digital delays that didn't use different read and write 
>addresses to vary the delay time, but limited the address range instead 
>(i.e. variable reset address for the address counter). This is of course 
>next to useless for delay time modulation, since it only takes effect when 
>the counter wraps around.
>
>>The technique that could be used is to run the memorychip as a
>>flexible buffer between two different clock domains (i.e. asynchronously)
>>which is a little more difficult to implement, but is really not that
>>much of a mystery these days (look in for instance the Xilinx appnotes).
>
>Two different clocks? To get pitch shift effects? Or what would this be 
>good for?
>
>Ingo


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