[sdiy] Delays: how?

[Ingo Debus]

Magnus Danielson wrote:
> Sorry for speaking digital design lingo... two different clocks does not
> necessarilly have to have different frequencies all the time. In digital
> design you need to know not only if things are of the same or different
> frequency, but you also want to know if things are synchronous or
> asynchronous. You can have two clocks which have different frequencies
> but is synchronous in relation to each other, which makes design simple.
> You can also have two clocks of nominally the same frequency, but which
> may vary only slightly in relation to each other. Then those clocks must
> be considered to be asynchronous in relation to each other, which can
> include synchronous relations under certain periods of operation. As soon
> as two clocks are not the same frequency and/or not being synchronous you
> consider them to be two separate clocks. The aspects which makes them
> different forces you to different amount of work to handle the situation.
> 
> Now, you could have a read and a write clock which nominally have the
> same frequency, but then you could vary the write clock such that you
> changes the phase difference between the clocks, such that the delayed
> time vary. This way you could make smooth adjustments of delay on sub-
> sample resolution. You can even have it under analogue control.
> 
> What you do is that you generate the write clock out of the read clock
> using a PLL. The PLL uses the buffer fill level as the phase detector.
> The delay CV is then used to compare the reference level, and the output
> of that comparision is sent to the loop filter. While this may sound
> crude, I know that you can make this become very stable. You get a very
> accurate delay control and you also get the pitch-shifting associated
> with varying the delay. In all this gives you much of the "feel" of an
> analog delay under CV control, but using modern component.
> I've build similar stuff before, so I am with comfort of this solution.

Ah, now I understand. This is really an interesting approach. The more 
I think about it, the more I like it. Are there any commercial delays 
that work this way?
So read and write sample rates are the same, and independent of the 
delay time, as long as the delay time is not varied. If the delay time 
is varied, i. e. modulated, one of the sample rates change, so the 
read and write pointers move closer together or further apart. The 
upper and lower limits of the sample frequency would affect the 
maximum rate of change of delay time, but not the delay time itself. 
Did I get it right?

But if you're using standard (not dual-ported) RAM chips, there has to 
be some arbitration logic to prevent that the read logic and the write 
logic tries to access the RAM at the same time. Isn't this quite 
complicated?

Also, what you call "buffer fill level" is, as I understand it, the 
difference between the two address counters. Calculating this 
difference on the digital side isn't trivial either, because of the 
two different clocks.

Ingo