[sdiy] Re: Daffy CMOS ASCIImatic

[Scott Bernardi]

I think the signal level has to do with the area of the V to I curve you are
on.  Here is a horribly crude hand drawn I-V curve:
http://members.attbi.com/~sbernardi/elec/fet_curve.gif. This is probably more
accurate for a JFET than a MOSFET, but the principle is the same.
The different gray curves occur at different values of Vgs; the one that give Id
= 0 is where Vgs exceeds the cutoff voltage; this is the switch OFF state.
Notice the parts of the curves where it is roughly horizontal; this is the
switch ON state. It occurs past the pinchoff voltage for Vds, represented by the
thin blue curve.
The voltage controlled resistance occurs in the relatively steep part of the
slope below the pinchoff voltage. Note that there is a different I to V slope on
the curves, meaning different resistance, depending on the Vgs value. But you
have to limit yourself to a low signal to get an approximate straight line here
(low Vds).

Scott Gravenhorst wrote:

> This is good info.  And it brings me to a question.  Considering
> the 4016 analog switch, the spec claims that a signal of 5v p-p
> is usable with Vdd-Vss of 10v, for 0.4% "distortion".
> They seem to omit a noise spec altogether for the 4016.  But to
> my question regarding:
>
> "FETs as linear VC resistors need a rather small signal level."
>
> Why do they recommend using a signal as large as half the rail
> to rail span?
>
> Is this because in the 4016 it is expected that the pass through
> transistors are either full on or full off?
>
> So it appears that the _4016_ (not my morphodite 4007 thing) can
> work with a fairly large input signal...  This spec is why I
> thought this might work.  But I really don't know what happens
> distortion/noise wise when the control signal is continuous and
> not 2 state digital.
>
> I get the feeling that I should toss this onto a breadboard and
> just try it.  The problem is that I really have little in the
> way of measuring performance such as noise unless it is so large
> that I can see it on my scope as being a significant proportion
> of the output signal.
>
> Thanks again, you people are wonderful.
>
> jhaible at debitel.net wrote:
> >Just a thought:=20
> >FETs as linear VC resistors need a rather small signal level.
> >OTOH linear amplifiers built from 4000 series CMOS chips
> >are not exactly low-noise, so they benefit from rather high signal
> >levels.=20
> >Both are good ideas, but I would not necessarily use them *together*.
> >
> >I have often thought how nice it would be to have a "low noise" version
> >of a 4007 or a 4069. Of course it would be possible to do similar things
> >with discreete transistors, but that's expensive, and the elegance of the
> >creative use of a low cost 4007 would be lost ...
> >(I think there used to be a - rather expensive - CA3xxx part with a CD4007
> >configuration, but I never checked this.)
> >
> >I have not thought this thru entirely, mind you. So I cannot quantify
> >"noisy" at this point. Maybe part of it just comes from the high resistor
> >values that are typical for linear 4000-series applications. (If you're
> >using small feedback resistors, they are loading the amp outputs, which are
> >just two current sources in open-loop case, more or less.)
> >
> >JH.
> >
> >
> >
> >At 19:07 28.04.02, Scott Gravenhorst wrote:
> >>Or a dual supply, +/- 7.5 Volts  and then the load goes to=20
> >>ground ?
> >
> >Right, something like that.
> >
> >>I thought about this, couldn't figure why...  I assume you
> >>mean to use the 2nd linear inverter like a cv preamp to this?
> >
> >The output of the "switch" would be run directly into the=20
> >inverting input of that invertor.
> >
> >>I don't get this.  Which input and why?  CV in?  I've seen=20
> >>this in single transistor units (drain to gate) but it's=20
> >>coupled with a resistor.  Is this a linearity improvement?
> >
> >If one uses such a configuration, the output of the two MOSFETs is=20
> >held at a constant potential. This should improve linearity.
> >
> >>Also, I looked at this again, and I think that if only one inverter
> >>is used, this can be made out of one 4007.  Powering it will have no
> >>effect on protection diodes turning on.  Only an analog signal out
> >>side of the rail-rail boundarys would cause problems.  Also I think
> >>the other pair of transistors could make another VC resistor that
> >>reponds reverse of the first.  VC pot?
> >
> >That would be interesting.
> >
> >Cheers,
> > Ren=E9
>
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--
Scott Bernardi
sbernardi at attbi.com