[sdiy] CMOS V.C.R. with 1V/Oct Response

[René Schmitz]

>What a great design! Nice job Mike!

I second that!

>One question that springs to mind is the signal levels. Will the resistors
>tolerate swings below Vss? Or does the signal voltage have to remain above
>Vss?

Its possible to use mosfets with swings below Vss, as long as the D-S diodes 
are out of conduction. Which is no problem with levels of 100mV. 

I wonder if the two resistor linearization method for the fets can be
applied to 
this circuit as well.

Cheers,
 René




-- 
uzs159 at uni-bonn.de
http://www.uni-bonn.de/~uzs159