[sdiy] FPGA multiplier

[Magnus Danielson]

From: James Patchell <patchell at cox.net>
Subject: Re: [sdiy] FPGA multiplier
Date: Sat, 06 Dec 2003 09:22:26 -0800
Message-ID: <5.2.1.1.2.20031206090655.00bc8d98 at pop.west.cox.net>

> Right now, I would say that the Xilinx Spartan 3 chips are you best bang 
> for the buck.  These chips are very inexpensive.  I would be willing to bet 
> that we are talking about $20 US for a fairly modest chip....(Spartan 3 
> chips start at 50,000 gates, if I remember correctly).  Also, the spartan 3 
> chips have dedicated 18x18 bit multipliers.

Not quite, but it is true that there is dedicated hardware which is rarely used
other than for the multiplier macros. This is normally unused features of the
slices which you can only use if you work some on it, but on the other hand
why? There is good macros which is easy to use.

> The 50K part has 4 of these multipliers, the 200K part has 12 multipliers 
> in it.....that is a lot of multipilers.  Plus, with a 200K part, you can 
> implement a DSP of proportions that 10 years ago you could only dream about.

I agree, the stuff you can do these days is really mindboggling and it comes
for a low price. The real limit is most of the times a combination of pushing
the most out of the hardware as while as being able to do it in a good coding
style and being able to engineering it. In the end it's your own ability that
puts the limit.

> Plus, you can download the Webpack for free and write the code in either 
> verilog or vhdl or schematic capture, or all three at once...it is a very 
> nice software package.

Do It Now!

> And believe me, 200K gates is an unbelievable number of gates.

Indeed.

> There is one drawback...you need to be very familiar with designing high 
> speed logic circuits.  Many of the klugey things you can get away with 
> using CD4xxx series logic will not work in a xilinx gate array.  The logic 
> in the spartan 3 can run up to about 300MHz, and the compilers will let you 
> do klugey things.

Well, yes... but many of the things you need to know is very simple and if you
learn to use the flexibility of VHDL the right way, then you can avoid stupid
errors and let the synthesis tool do it for you.

Here is a few rules of thumbs in short-form:

1) Don't ever use latches, use only flip-flops. The reason is that an open
   latch makes the maximum delay before and maximum delay after the latch to
   become the longest combinatorial path, those causing the maximum frequency
   to become much lower. Forget about latches and think what you can do with
   clocked flip-flops. For most designs (for a beginner) a
   Register-Transfer-Logic view is sufficient and a good view, i.e. you have
   clocked registers (clocked in a common clock) and those feed the inputs of
   combinatorial logic (i.e. normal and, or, not, xor, muxes etc. gates) and
   the output of the combinatorial logic feeds the input of clocked registers.

2) Avoid or reduce the amount of asynchronous flip-flops. Often there is
   synchronous solution which you can test out well. There often need for some
   asynchronous handling, like going between two synchronous clock domains
   (which is asynchronous to each other), but you want to make any such
   transition at as few places as possible. Asynchronous designs is more
   difficult to do than synchronous design and testing is even more difficult.

3) Use the flexibilities of the VHDL language to make the code readable rather
   than what makes "obviously minimal logic" because the logic powers of the
   synthesis tools is such that they will do the logical reductions correct and
   most of the times better than you anyway. You can however make code which
   mapps well to a particular hardware, but that isn't the same style of
   reductions that you might have used for CMOS/TTL designs.

4) In VHDL you have signals and processes. The signals is the equalent to a
   signal network between components, and the processes is really the equalent
   of the functionality inside a chip (say a flip-flop, gate, memory). Can you
   divide all your functionality into process with signals to communicate
   between these, then there's hope. While VHDL allows for variables which is
   shared between processes, which works when you _simulate_, it is not to
   recommend for synthesis, so don't use it.

5) In VHDL you group functionality (as found in processes) into "components"
   (the term component has a specific meaning in VHDL, which might be
   enligthning). For such a grouping you declare an entity, by providing the
   "ports" of signals in and out of the entity, basically the pins of a
   component. You might also provide various configuration values in the form
   of constants named "generics". For such an entity declaration one or more
   architectures be declared, basically providing one or more implementation of
   this entity. It is in the architecture that you stuff the process
   descriptions.

6) Make use of the generics in order to parameterize designs, so that you can
   write say a D-flip-flop onces but for various widths, and then assign the
   a parameter in order to adapt which variant fits your need.

This is just from the top of my head. I've intended to write down more of this
stuff, since I have long had the feeling that people make it more difficult
than it has to.

> Still, using an FPGA is the way to go...I have many ideas I would like to 
> try myself...time is my only limiation... :-(

WHY do I recognice that so well?

Cheers,
Magnus