[sdiy] Parallel processing clock design question

[jbv]

Roman :

> if it's for sound synthesis, why not use separate
> XTALs and sync the micros using interrupt at sample
> rate. If all communication between them happens
> just after interrupt, they will be synced exactly
> on instruction. Even without that in mind, at 48ksps,
> micros can desync (is that a word?) no more than
> 1 clock cycle at 0.1% initial frequency accuracy.
> Common XTALs are better than that AFAIK.
>
> And having only 48kHz signal on whole PCB is much
> easier to handle than 1000 times higher frequency.
>

Yes, that's exactly what I'm planing to do : sync all
uCs with a 48KHz interrupt signal.

But before sync, I need to think how to clock those
uCs, hence my original question.

As for achieving clock and sync at the same time,
since the 1st day I started brainstorming on this
project (more than 2 years ago actually), another
idea crossed my mind : if I use a Crystal CS5360
as 24 bits A/D, in master mode this chip delivers
a signal which is 256 * Fs (256 * 48KHz = 12.288MHz).
Then I could use that signal both for clock & sync of the
uCs :
- it's not difficult to divide by 256 to get back to 48 KHz
(I could also route 2 signals and avoid extra chip for
dividing by 256)
- to get a clock signal closed to 75MHz, I could use a
clock multiplier such as the ICS501 to multiply 12.288MHz
by 6...

Has anyone already used these little things ?
http://www.icst.com/products/oscillators.htm

Thanks,
JB