[sdiy] Parallel processing clock design question

[Martin Fay]

JB wrote:
>Here's how I see things : each uC will run a forever loop just
>doing nothing (waiting for interrupt signal actually). When
>interrupt occurs (at 48KHz), then the real task begins

This is barely different from the polling version, but polling is
simpler than using an interrupt.

loop on (is sample indicated)
process sample

vs

loop on (nothing)
<- interrupt
process sample

The polling version will be more forgiving when there is too much work
to complete though, just missing a sample as opposed to reentering.

Note that it's typical for audio processing applications on a PC to
simulate the polling situation using threads as opposed to using an
interrupt directly.


Martin

| VAZ Modular virtual analogue modular synth
| VAZ 2010 virtual analogue synth
| www.software-technology.com