[sdiy] Parallel processing clock design question

[René Schmitz]

jbv wrote:
> I agree that this is some kind of brute force method, and may be
> not the most elegant design, but it might work quite well.
> The advantage of this method is that, when interrupt starts, there's no
> need to save registers and such, since the main task is doing nothing.
> Furthermore, the uC I'm planing to use (the Scenix SX) has a very
> short interrupt rersponse time (50 to 60 ns IIRC).

Well most uCs handle saving the PC on their stack at least, so there
will be a delay of a couple of cycles at least.

Worse still, when executing a multicycle instruction the interrupt 
might be delayed after that instruction has completed.

Here polling your syncing signal has a distinct advantage of shorter and 
consistent response time. And if you're going to "burn off" the unneeded 
performance anyway, you don't loose anything.


Cheers,
  René

-- 
uzs159 at uni-bonn.de
http://www.uni-bonn.de/~uzs159