[sdiy] S&H problems

[David Reichert]

Hi everyone

I'm currently trying to put together a sample and hold circuit, I'm not
having any trouble getting it to sample, but I'm quite struggling with
the  holding end of things!

Seems to me that the trouble is in the switch, it's obviously leaking
back through the switch. I'm using a JFET, The drain is the output,
source as the input. I have a 1M resistor connected between the source
and gate. As well, I have a diode connected with the anode connected to
the JFET gate and the cathode is the controller input terminal.

Both the input and output are buffered, which leads me to suspect that
the leakage is through the gate, but I have not confirmed this. This is
backed up by the fact that when I tried removing the source connection
before closing the switch, the capacitor still discharged.

I've tried several different types of FETs, switching the roles of the
source and drain, adding a short delay before the gate switches off (in
case it's a timing problem) and none of these has helped the situation.

If anyone has some advice, it would be much appreciated!

Thanks in advance,
Dave