[sdiy] S&H problems

[harrybissell]

Grant Richter wrote: (and I snipped)

> Every op-amp or voltage buffer has to draw SOME bias current (or leakage).
> The voltage buffer on the cap HAS to be a FET low bias current type like a
> TL08x or a CA3140. A 741 or LM324 will NOT work.

The LM324 is the worst possible choice... the PNP inputs assure that the
bias current frows 'out' of the input... making your hold cap climb to the
supply
voltage during the 'hold' phase. There is an app note to null the bias
current...
not worth it imho. Use a TL07x series or CA3140...

> Also, use a big enough cap
> for the sample cap. 0.01uF or 10,000pF is a good compromise between hold
> time and sample time.
>
> See the data sheet for the LF398 sample and hold chip.
>
> http://www.national.com/pf/LF/LF398.html
>
> The chip is so cheap and easy, it make sense to just use them unless you
> need some special features (like slew rate limiting inside the S/H for
> probability control).

I see the LF398 as a cheap and dirty S/H... Good for a one chip solution where
droop really does not matter too much... I think you can easily build a discrete

S/H that will outperform it (but not a smaller one :^)

H^) harry

>
> Try Jameco, Mouser etc.