[sdiy] DRAM question(s)

[fmg]

I have a shoe box plenty with 30pins DRAM SIMMs. I can't see them
unemployed and sleeping, dreaming for a better life, and decided
to make a multiple digital delays bank with them.

I plan to put a wide control of time, from milliseconds to several
seconds and use the bank as a module, among other modules within
the boundaries of the synth and not as a post FX.

I spent a week working in a discrete sigma-delta with (relative)
decent results. Now that I'm trying to make the timing for the
DRAMs some problems arises.

As I see in datasheets to perform a read-modify-write cycle /OE
must go low while /WE was_and_is high to read, then /OE MUST go high
and THEN /WE low to write. This is clear and seem to be mandatory
as I see in datasheets. But there is a little problem, /OEs are
grounded in SIMMs and there is no way to put a high on them.

My question is: it's posible to perform a read-modify-write with /OE
always low? (read after a /CAS delay then switch the io pin for input
and apply /WE) <- isn't this a paradox for the RAM io stage?

Or, shoud I scan the entire RAM writing (in early write mode) and
when finish, scan it enterely again reading? (with a second RAM doing
the opposed for a continuous audio/signal stream?

Did 386/486 PCs never make use of read-modify-write mode?
or can these datasheets specs be ignored in favor of other
undocumented features?
Should I cut the tiny traces of the SIMMs to recover /OE ?

These timings with a common pin for input/output is a little hard
to me to understand.

This is an ambitious project for me, I imagine delayed VCAs, a VCO
FMized by itself and twisting as time passes, envelopes in a time
other than where/when they should be, etc, etc. I think it's like
having a door open with full access to a parallel world  ;-)

In the other hand, sorry if I show myself stupid asking this, I'm
a complete ignorant of RAM mysteries, and sinking and sinking
deeper in the dark.

Any floating object will be appreciated  :)


Fabio Gonzalez