[sdiy] new schematic posted

[Peter Grenader]

Two things you might want to consider, always nice in a lag:  stick an LED
in at the non-inverted output -and- how about a switch for parallel caps
which increases the value at AR2 (range)?

should I shad up now? (Magnus says yes, always....)

ha!

- P





harrybissell wrote:

> Hi Ingo...  (inline)
> 
> 
>> Nice circuit. I must confess, it took me a while to find out why the
>> output of AR3 is tapped off *after* the diodes and not directly from
>> the opamp's output. This is to compensate for the diode voltage drop,
>> right?
> 
> right.
> 
>> 
>> But doesn't this cause some interaction between the attack and the
>> decay pot if the shape pot is not in one of its end positions? As I
>> understand it, one one of the diodes conducts at a time. Say, the
>> attack diode conducts and the attack pot is set to some high
>> resistance. Isn't there some voltage fed into the integrator via R9 and
>> R10 and the decay pot? Unless the shape pot is in an end position, in
>> this case this path would be shorted to ground or virtual ground. But
>> if the shape pot is in center position, R9 and the two halves of this
>> pot form a voltage divider. So the decay pot would have an influence on
>> attack too.
> 
> Hmmm. I have not noticed any interaction.  Both sides of the shape pot are
> at ground... The worst case would have to be with the pot at center
> rotation...
> each side would be 5K... in parallel that is 2.5K to ground.  The 20K /
> 2.5K
> divider would limit the effect of feeding back through one 20K... past the
> 2.5K to ground, through the other 20K... and through whatever remains of
> the decay pot.
> 
> You could bring the resistor levels up (proportionally) and the effect
> would be still
> less... but it may be that they do interact a little. I'll try and look for
> it.
> 
>> Another question, as I see it, in linear mode (wiper of shape pot at
>> ground) AR3 is overdriven (no local feedback). Can't it latch up?
> 
> I suppose it could... but there is always the feedback from the integrator
> as well.  I've built a log of linear lag circuits with this technique...
> and have not seen
> a latch up.  If you were going to have one, it would probably be at some
> negative
> input voltage (imho).
> 
> Choosing a different opamp could cure that if it was found to be a
> problem...
> 
> Thanks for the comments !
> 
> H^) harry
> 
>