[sdiy] CMOS clock inputs.

[Dave Kendall]

Thanks Ken.

Will try that now...

cheers,

Dave.

on 1/4/06 12:33, Ken Stone at sasami at hotkey.net.au wrote:

> 
>>> do you have a pull-down/pullup resistor?
>>> Ken
>> 
>> Oops!
>> 
>> The clock advances on a Low-High transition, so I guess it should be
>> connected between CLK and GND. What would be a good value to start with?
>> supply is 0V +15V.
> 
> 10k or 100k. It doesn't really matter.
> 
>> I've had a look in some text books, and an unconnected TTL output floats up
>> to HIGH, but it doesn't mention what CMOS inputs and outputs do...
> 
> CMOS are capacitive - the float, and are affected by the smallest stray
> field, so can be quite unpredictable.
> 
> For a rising edge, I would use a pull-down resistor. I would also put at
> least 1k between the input and the switch (remember that it will form a
> voltage divider with the pulldown, so don't over do it). The switch can then
> simply disconnect/connect to +15 with no zero volt connection needed because
> the pulldown is already doing this.
> 
> Ken
> 
> _______________________________________________________________________
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