SV: Re: [sdiy] Xilinx 3E webpack and its gotcha's!

[Eric Brombaugh]

Paul Maddox wrote:
> that would be superb, if a couple of the 'pro' VHDL people could write 
> a couple of 'hello world' examples.

I guess that rules me out since I use Verilog. :)

Seriously though, what's the consensus on HDLs? I know that for a long 
time VHDL was more popular than Verilog in the FPGA world, but from what 
I can tell the tools are agnostic on that point today. Verilog was more 
popular in the ASIC design world, but due to the increased popularity of 
FPGAs, a lot of us old-time ASIC designers are now finding ourselves on 
the other side of the fence.

I've never seriously tried to do VHDL, but looking at the code always 
makes my head hurt. When I compare code snippets in the FPGA 
documentation that demonstrate how to do something in both languages, 
the VHDL examples are always 2-3x longer than the Verilog ones.

Based on that, I guess I'm surprised that more beginners aren't drawn to 
Verilog over VHDL.

Eric