SV: Re: [sdiy] Xilinx 3E webpack and its gotcha's!

[Paul Maddox]

Karl,

I think the schematic capture is a perfectly valid way to get going quickly, 
and you can then look at the code and try to look at how it all works.
Magnus is right in that it won't give you the best code, nor will will it be 
as quick as compiling VHDL.

Paul

----- Original Message ----- 
From: "karl dalen" <dalenkarl at yahoo.se>
To: "James Patchell" <patchell at cox.net>; "Magnus Danielson" 
<cfmd at bredband.net>; <ebrombaugh at earthlink.net>
Cc: <synth-diy at dropmix.xs4all.nl>
Sent: Wednesday, June 14, 2006 10:04 PM
Subject: SV: Re: SV: Re: [sdiy] Xilinx 3E webpack and its gotcha's!


>I dont want to use verilog shit or VHDL shit i want to use the schematic
> shit in webpack, i dont have any time to learn just another language, 
> shit!
>
> But Magnus has  told me not to use the schematic shit of webpack shit
> because it generates verilog shit code at compilation and linking time 
> shit
> in GCC with bananas in my neighbours ..........!
>
> Shit!
>
> KD
>
> I get aids and my hair curls when i hear you folks talking
> about all those ADHA,VHDB,BDPE, PCB, IEEE,CMJRE !!
>
>
> -- James Patchell <patchell at cox.net> skrev:
>
>> I use both....they both do the same thing...they both generate the same
>> logic...so, just pick one.
>>
>> I myself...when given a choice, I use Verilog...all of the jobs I have 
>> done
>> have required Verilog...but who knows..
>>
>>
>> At 04:33 PM 6/14/2006 +0200, Magnus Danielson wrote:
>> >From: Eric Brombaugh <ebrombaugh at earthlink.net>
>> >Subject: Re: SV: Re: [sdiy] Xilinx 3E webpack and its gotcha's!
>> >Date: Wed, 14 Jun 2006 06:06:23 -0700
>> >Message-ID: <449009CF.2060803 at earthlink.net>
>> >
>> > > Paul Maddox wrote:
>> > > > that would be superb, if a couple of the 'pro' VHDL people could 
>> > > > write
>> > > > a couple of 'hello world' examples.
>> > >
>> > > I guess that rules me out since I use Verilog. :)
>> > >
>> > > Seriously though, what's the consensus on HDLs? I know that for a 
>> > > long
>> > > time VHDL was more popular than Verilog in the FPGA world, but from 
>> > > what
>> > > I can tell the tools are agnostic on that point today. Verilog was 
>> > > more
>> > > popular in the ASIC design world, but due to the increased popularity 
>> > > of
>> > > FPGAs, a lot of us old-time ASIC designers are now finding ourselves 
>> > > on
>> > > the other side of the fence.
>> >
>> >The "design world" is infact quite divided still. There is no winner and 
>> >I
>> >think the discussion as such is dated. I use VHDL and so does several
>> others.
>> >
>> > > I've never seriously tried to do VHDL, but looking at the code always
>> > > makes my head hurt. When I compare code snippets in the FPGA
>> > > documentation that demonstrate how to do something in both languages,
>> > > the VHDL examples are always 2-3x longer than the Verilog ones.
>> >
>> >While I have looked at many Verilog sources just to find them 
>> >unreadable.
>> >Face it, the other language looks like the ugly child depending from 
>> >your
>> >own preference, but that doesn't boil down to a real truth. We do large
>> >designs
>> >in VHDL and it works well. The whole issue about "2-3x longer" is IMHO 
>> >pure
>> >bogus and doesn't really measure anything about usefullness.
>> >
>> > > Based on that, I guess I'm surprised that more beginners aren't drawn 
>> > > to
>> > > Verilog over VHDL.
>> >
>> >After what I've seen I am suppriced so many still persists on using 
>> >Verilog.
>> >Neither of these personal views means anything in the end. They are just
>> >different views based on different experiences, gain from different
>> >backgrounds
>> >etc. VHDL works splendid for both small and large projects. As for how
>> Verilog
>> >works, I assume people would feel the same way.
>> >
>> >Last time I looked into the Verilog LRM (I have a hardcopy from IEEE) I
>> >concluded that it was a not too well defined languague and infact I had 
>> >to
>> use
>> >some of my more obscurer knowledge in C and interpolate with what the 
>> >LRM
>> said
>> >in order to conclude on the correctness in a certain Verilog model which
>> >someone claimed to be invalid Verilog and was quite supprised to find 
>> >that
>> the
>> >golden reference actually accepted. In contrast is the VHDL LRM actually
>> quite
>> >complete, but it is on the other hand hard to correctly interprent 
>> >unless
>> you
>> >spent some time with it.
>> >
>> >So, there is no and will never be any real winner in the Verilog vs. 
>> >VHDL
>> >battle. These are the two languagues that has to be supported and one 
>> >cannot
>> >make the assumption that one is better than the other.
>> >
>> >Cheers,
>> >Magnus
>>
>>          -Jim
>> ***************************************************************
>> Come to the 2006 Pacific Southwest Synth DIY meet
>> June 10, 2006 at the Goleta Library....
>>
>> Details:
>> http://www.oldcrows.net/~patchell/synthdiymeet.html
>> ***************************************************************
>> http://www.oldcrows.net/~patchell
>> http://www.noniandjim.com/
>> ***************************************************************
>>
>>
>>
>
>