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Re: [AVR-Chat] Re: Debugging a ATmega48V - what's going on? - I found it!

2007-11-14 by Tim Gilbert

Yes, I use it during the layout process as well but have learned two things:

1: automatically have Eagle include the date and file name on the actual board; 
2: always run ERC and DRC one more time before sending the files to the board house!  


Regards,

Tim Gilbert
JEM Innovation Inc.
303-926-9053 (office)
303-437-4342 (cell)
720-890-8582 (fax)
www.jeminnovation.com
www.pdksolutions.com

  ----- Original Message ----- 
  From: Graham Davies 
  To: AVR-Chat@yahoogroups.com 
  Sent: Tuesday, November 13, 2007 6:02 PM
  Subject: [AVR-Chat] Re: Debugging a ATmega48V - what's going on? - I found it!


  --- In AVR-Chat@yahoogroups.com, "Richard Cooke" <rcooke@...> wrote:

  > ... Eagle will allow you to make
  > a connection while laying out the
  > PCB even if the schematic doesn't.

  I want to join Tim in saying that you really must use the Design Rule 
  Checker. Eagle won't actually "allow you to make a connection" that 
  isn't in the schematic. But, it will allow you to add a trace, which 
  is a different thing. Connections are "air-wires" that you remove by 
  routing traces. If you add a feature (such as a trace) directly, Eagle 
  assumes you know what you're doing. Use the DRC to have it check that 
  the board will come out right.

  Unlike Tim, however, I have never found a problem at the last minute 
  with the DRC. That's because I run it over and over again as I work up 
  the design. You might consider this also as it avoids having a whole 
  bunch of stuff to deal with at the end.

  Graham.



   

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