AVR-Chat

When in slave mode, and the /SS is driven high, the data sheet says: "...the SPI slave will immediately reset the send and receive logic, and drop any partially received data in the shift register."

OK, but does the SPIF flag get set?

Would I be correct in assuming that it doesn't and that I would have to monitor both SPIF and the /SS status to catch both end-of-transmission possibilities?

Thanks,

Hal