AVR-Chat

On Thu, Oct 11, 2012 at 6:08 PM, bayramdavies <Yahoo37849@ecrostech.com> wrote:

> Yes, it is extensively used in digital circuits too, but it's a bad idea. The analysis that proved to me that it was a bad idea was done in the context of using surface-mount ceramic chip capacitors in the bypassing of digital circuits. I don't know if there are other considerations for UHF and microwave. Also, years ago you could only get small values in the smallest, low inductance, packages, so there was a counter-argument for paralleling different values.
>
> A modern ceramic chip capacitor has a parasitic inductance of no more than the equivalent-sized piece of wire. You can get 0.1uF and higher >values in 0402 size. The effectiveness of such a bypass capacitor is usually determined by how you connect it to the device pins and power and >ground planes.

It has to do with the self-resonance of the package.  Different
capacitance values may have the same package self-resonance, for
packages of the same size:

http://www.sigcon.com/Pubs/news/1_17.htm

Summed up in Intersil App. Note 1325:
   http://www.intersil.com/data/an/an1325.pdf

"Since the same package was used for each of the capacitors,
their high frequency responses are the same. Effectively, this
negates the use of the smaller capacitors!"

Articles by Howard Jonson on the subject:
http://www.sigcon.com/Pubs/pubsKeyword.htm#bypass%20capacitors


For anyone that is really into this kind of stuff I *STRONGLY*
recommended subscribing to the
Compliance Club, and reading all 102 (current issue) back issues:

Journal Issue #55 and #56 2004 explains the issue and the issues of
layout that I've never seen described anyplace else:

http://www.compliance-club.com/journal_article.aspx?artid=138 section
2.6 to 2.9.

[Note the pop-up at the bottom of the screen that forces you to check
a box to allow cookies, if you don't you can't subscribe.]

Every layout I've ever seen puts the different values capacitors in
the same physical orientation next to each other.
This fails to account for magnetic flux interference between the packages.

Self-resonance (package), ESR, ESL, capacitance value, magnetic flux
(layout), frequencies of interest, number of board layers, all have to
be accounted for, which means it is not as easy as paralleled values
is good or paralleled values is bad.  Makes this job such fun...


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