AVR-Chat

Zack Widup wrote:
> 
> Hi Russell,
> 
> Can you tell me more?
> 
> Zack W9SZ
> 
> On Wed, 30 Mar 2005, Russell Shaw wrote:
> 
>>Multiple groups thin out the expertise. I could have told yas years ago
>>about receiver design, dds spurs, and what to do with'em.

The spurs are caused by capacitive spikes generated by each dac pin. The
lowest LSB has an equal glitch level as the MSB, so the biggest total
glitch energy happens when most of the pins switch in the same direction.
When an output pin switches, the small spike of capacitive current also
puts a pulse on the grounding bond wires of the dac chip, which feeds
thru to the other output pins too.
With this, you can make a program that computes the spur levels for any dds
clock frequency and output frequency setting. Then you can find a band
where the spurs are low. Eg, you might use a dds clock of 50MHz and find
a 100kHz BW low-spur band around 1-2MHz. You then mix this into a conventional
pll system, so that the dds gives you the sub 100kHz step capability, and
the conventional pll runs with a 100kHz reference. The conventional pll
is used as the first LO, such as 45-75MHz for a 0-30MHz HF receiver.
This sort of circuitry involves a fair bit of filtering and mixing
that can take a while to design for the uninitiated.

Without the dac problems, a properly designed dds only has spurs
due to the usual finite bit quantization resolution. This can be
made arbitrarily small inside a dsp program, but in hardware, the
dac problems take over.