AVR-Chat

On Apr 20, 2005, at 6:34 PM, arhodes19044 wrote:

> It has got to be a simulator issue.  I agree that only one interrupt
> will get triggered for an individual timer function.

I don't follow what you are saying.

> It is just that I can clearly see the TC0 overflow interrupt get set
> as the TC1A OC interrupt is cleared.

Something I found earlier this week with timer 3 was that it would fire 
as expected on input capture but my output compare event would never 
trip. Not until I wrote to TCNT3 in my input capture routine, which 
happens to be where I enable the output compare.

Doesn't appear that TCNT3 ever runs until its written, and that it 
stops when an IC3 or OC3 event occurs. I'm using mode 4, CTC, OCR3B for 
compares.

Thats a heck of a note because if I wanted to let TCNT3 free run and 
generate overflow interrupts, my use of OC3 prevents it from 
overflowing. The easiest way to write TCNT3 is to zero it, then OCR3B's 
value is constant. On other architectures in the IC IRQ I write the sum 
of a timer plus an offset to a compare register to indicate when I wish 
the OC IRQ. Didn't seem to work with my 128.

Specifically have AC zero crossing detector connected to IC3, am 
driving a triac gate from the service routine, then using OC3B to tell 
me when to turn it off.

--
David Kelly N4HHE, dkelly@HiWAAY.net
========================================================================
Whom computers would destroy, they must first drive mad.