Well, that was an interesting reply. 5V is NOT the high level for TTL. Never was. It's not the high level for CMOS either. 5V is the VCC level for TTL though. Each logic family determines it's low and high thresholds. TTL levels are well defined here: http://media.iet.hist.no/lab3ee/avgrensa/74xx.htm Then there's the more modern LSTTL http://media.iet.hist.no/lab3ee/avgrensa/74lsxx.htm Good comparison here: http://www.interfacebus.com/voltage_threshold.html The why of it, is that this is how the inputs of the gates are designed, and the difference between the high and low threshold gains you noise immunity as you increase it, but it costs you power, since you spend more in resistive dissipation, and charging/discharging gate capacitances.
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Re: logic levels..
2005-09-12 by Dave VanHorn
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