AVR-Chat

On Sat, 2005-10-29 at 00:14 -0700, Larry Barello wrote:
> I am trying to mate an AT45DB041B (4mb data flash) with an ATMEGA32.
> The interface seems straightforward: SPI mode 0 (CPOL = CPHA = 0), but
> if I follow the proscribed "DataFlashReady" algorithm the chip only
> returns "not ready (e.g. 0x4E).

   This brings to mind a question that popped into my head this morning.
I was reading the latest issue of EE Times (free trade journal, highly
recommended, www.eetimes.com), foudn an article on OneNAND RAM.  Seems
Samsung has developed a melded terchnology which offers the best
attributes of both Nor and Nand Flash technologies, plus a relatively
fast erase time (108 MB/s reads, 10 MB/s writes, and 64 MB/s erase
perforance, and available in 128 Mb through 4 Gb sizes).  Also comes in
at about 30% less expensive than Nor Flash RAM (which is still more
expensive than Nand, but the OneNand technology offers far superior
performance).

   In any case, per the article, apparently the interface to Nor RAMS
and Nand RAMS is different (e.g., not compatible).  The OneNand uses the
Nor-style interface.  Does anyone here have eany experience yusing Nor
Flash on an AVR?  How is it done?

   For more informaiton on OneFlash, see www.samsung.com/semi/onmenand

Tom