AVR-Chat

Most SPI EEPROM's need the write enable to be set, which is another command 
that must be shifted into the part before sending the WRITE command.  The 
enable may also be cleared on CS going high during the two commands.

Otherwise, nothing will happen.  Check the datasheet.

Larrie.

>   Date: Sat, 29 Oct 2005 00:14:42 -0700
>   From: "Larry Barello" <yahoo@barello.net>
> Subject: Atmel Data Flash
>
> I am trying to mate an AT45DB041B (4mb data flash) with an ATMEGA32.  The
> interface seems straightforward: SPI mode 0 (CPOL = CPHA = 0), but if I
> follow the proscribed "DataFlashReady" algorithm the chip only returns 
> "not
> ready (e.g. 0x4E).
>
> I.e.:
>
> Void WaitDataFlash(void)
> {
> FLASH_CS(TRUE);
> SPI_Write(0x57); // SR read command
> While(!(SPI_Read() & 0x80))
> ;
> FLASH_CS(FALSE);
> }
>
> Has anyone experience with this chip and give any sage advice?  I have 
> tied
> /reset and /wp to VCC.  /CS is controlled by a port bit and the rest of 
> the
> SPI crew are attached to their respective pins.
>
> Have I misinterpreted what SPI mode 0 is?  I previously wrote routines for
> some Atmel EEPROM chips and it worked pretty much first time.  The Data
> flash routines are even simpler, but, of course, they don't work :(
>
> -----------
> Larry Barello
> www.barello.net
>