AVR-Chat

At 12:42 AM 8/04/2006, you wrote:
>But you don't really need to CLI till just before the SBI EECR.
>That's the only part that has to be atomic.

 From the Data sheet:
------------
The examples assume that interrupts are controlled (e.g., by 
disabling interrupts
globally) so that no interrupts will occur during execution of these functions.
------------
so in theory you could/should disable interrupts before you enter the 
routine even though
it is stated that:

 From the Data sheet:
-------------------
1. Wait until EEWE becomes zero.
2. Wait until SPMEN in SPMCSR becomes zero.
3. Write new EEPROM address to EEAR (optional).
4. Write new EEPROM data to EEDR (optional).
5. Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR.
6. Within four clock cycles after setting EEMWE, write a logical one to EEWE.
..................
Caution: An interrupt between step 5 and step 6 will make the write 
cycle fail, since the
EEPROM Master Write Enable will time-out.
-------------------
so as a minimum the above applies as you correctly state above. There 
would be no point
to disable ints while testing the EEWE.

however the recommendation is:

 From the Data sheet:

---------------
It is recommended to have
the Global Interrupt Flag cleared during the four last steps to avoid 
these problems.
--------------

>This does assume that your ISR preserves Z

I'm very careful in my ISRs to preserve ALL registers used
within. Sure miss the automatic register save of the HC11
though. :-)


Regards

John Samperi

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