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Hello: I hope I can help.  I have 40 years of electronic experience. The IRL520 is a hefty device, rated at 100V @ 9.2A.  BTW - what type of solenoid requirements are involved - high current draw, high mechanical load, repetition rate, etc.?  Do you really need to use this type of FET?   In my opinion, I think that the design can improved by controlling the current flows involved, so as to minimize spikes, etc.  The reversed biased diode to 12V is OK.  If you want, use a 'fast' (Shottky) diode to help quench the circuit.  Altho it is always best to quench at the source (the solenoid, in this case), one can also place components in a way that have 'preferrential' current paths.  The inherent diode that is part of the FET (Drain to Source) should be adequate for that current path, as it is at least as good as the FET itself.   The way to do this is to (mentally) divide the circuit into two parts; a low current (the gate circuit) and a high current (the solenoid).  'Pick' a 
point (constructionally) for the power and the ground.  On one 'side' of this 'point' is the low current and on the other side is the high current.  Between the two points, add an electrolytic (~100uf), bypassed with a .1uF.  The best place to 'divide' the circuits is right at the electrolytic leads.  (I speak from experience, as I have dealt with this type of problem before.)  This approach can be considered as being 'nodal', where a node (point) is chosen and not 'moved' for the current path involved.  As there are two circuit 'loops' (low and high currents), then they must share the common nodes involved.  Uncontrolled circuit paths (no nodes) create complex current paths, leading to problematic designs.  Think of the uncontrolled paths as a ladder array of resistors, with different connections placed anywhere - the currents get complex very rapidly.   The other advantage of the 100uF, is that it provides a low impeadance source for supplying pull-in current and acts as a 
low impeadance 'load' for the quench aspects.  Cool! If you keep all of the solenoid currents on that side and all of the currents for the gate drive on the other side, then there should be no real issue with driving the circuit.  This FET has a gate capacitance of about 490pF - not bad for the device, actually.  Otherwise, your use of the pull-down resistor on the gate is commendable, as most engineers overlook that subtlety entirely.  However, you should have a small resistor (~10 Ohms) and maybe a ferrite bead in series with the gate.  Rise and fall times are important for driving the FET gate - make sure that the uP, or other circuits not shown in your schematic, are capable of driving the gate properly, especially if you need fast pull-in and drop-out times for the solenoid.  If the gate signal is too slow, then the solenoid performance will suffer and the FET will dissipate excessive power while ramping up and down during the on and off states.   A circuit I designed 
many years ago resolved all of these problems and was very, very quiet from a digital and analog point-of-view.  If you decide that the problems are unresolvable, then you might consider using an opto isolator driving the FET, which might help, but certainly at higher cost and more parts, too.Divide and conquer! Good luck!

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