AVR-Chat

At 07:43 AM 25/02/2009, you wrote:
>GICR  |= (0<<INT0)|(1<<INT1);   // Disable INT0, Enable INT1

Remember that 0<<xx does NOTHING. :-)

You need to disable INT0 with

GICR  &= ~(1<<INT0);

Then enable INT1 or set up a mask in a uint8_t with the
bits you want and then

GICR  = mask;

Oh what a tangled web we weave when we first plan to use C....


Regards

John Samperi

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> Remember that 0<<xx does NOTHING. :-)


Right, thanks, but that isn't my latency problem.

It may be that GCC is saving "the world" before it enters my code..
@$!@$@#!$@#%$@%$
That would seem to be roughly the right order of magnitude.. 32 pushes..

In ASM, I'd have reserved a couple of registers specifically for the
ISRs, and another one for SREG, so getting in and out would be like
this:

ISR:
     in STEMP,SREG

     (ISR code, rarely needing to push anything at all..)

     out SREG,STEMP
     reti