AVR-Chat

Hello,

I need to generate a pulse of some length and plan to use Timer 1 on a ATMega644p in normal mode (0).

So I set 

 TCCR1A = 0b10100000; //This sets PD5/4 do be OC1A/B, to be cleared on Compare-Match
//                ||||||||
//                ||||||--WGM11, WGM10 (00) Normal Mode. Also set WGM13:2 in TCCRnB to 00
//                ||||--   Reserved, must be 0
//                ||--    COM1B1, COM1B0: 10 = Clear OC1B on Compare Match. Set at Pulse Start
//                --       COM1A1, COM1A0: 10 = Clear OC1A on Compare Match. Set at Pulse Start

    PORTD |= _BV(PD4) | _BV(PD5);    //OC1B, OC1A as  outputs 

The plan is to set OC1A/B (PD5/4) High before I start the timer and have the timer clear them on Compare Match.

My problem is: How do I set OC1A/B to High, as they no longer "respond" to commands sent to Port D?
I tried:
PORTD |= _BV(PD4) | _BV(PD5); to no avail.

Any help appreciated, thanks.

Cat
 		 	   		  

[Non-text portions of this message have been removed]

To answer my own question, I found a way, but is it the best/easiest?

TCCR1A = 0b11110000;    //Prepare so that next command sets OC1A/B HI (set on Output Compare)
TCCR1C = 0b11000000;    //Strobe - Forces an Output Compare for a/b so line above makes them HI


> To: avr-chat@yahoogroups.com
> From: catalin_cluj@hotmail.com
> Date: Tue, 6 Oct 2009 13:39:59 -0600
> Subject: [AVR-Chat] Help setting OC1A,B HI on ATMega644p, please.
> 
> 
> Hello,
> 
> I need to generate a pulse of some length and plan to use Timer 1 on a ATMega644p in normal mode (0).
> 
> So I set 
> 
>  TCCR1A = 0b10100000; //This sets PD5/4 do be OC1A/B, to be cleared on Compare-Match
> //                ||||||||
> //                ||||||--WGM11, WGM10 (00) Normal Mode. Also set WGM13:2 in TCCRnB to 00
> //                ||||--   Reserved, must be 0
> //                ||--    COM1B1, COM1B0: 10 = Clear OC1B on Compare Match. Set at Pulse Start
> //                --       COM1A1, COM1A0: 10 = Clear OC1A on Compare Match. Set at Pulse Start
> 
>     PORTD |= _BV(PD4) | _BV(PD5);    //OC1B, OC1A as  outputs 
> 
> The plan is to set OC1A/B (PD5/4) High before I start the timer and have the timer clear them on Compare Match.
> 
> My problem is: How do I set OC1A/B to High, as they no longer "respond" to commands sent to Port D?
> I tried:
> PORTD |= _BV(PD4) | _BV(PD5); to no avail.
> 
> Any help appreciated, thanks.
> 
> Cat

 		 	   		  

[Non-text portions of this message have been removed]

hi.
 
>One plan could be to set the port operation as normal (COMnA1/COMnB1/
COMnC1 - COMnA0/COMnB0/COMnC0) to 0, set the compare interrupt bit and write an interrupt handler on compare match, when the interrupt occurs, then set the ports as desired. There will be a degree of interrupt latency especially if there are interrupts occuring, this latency will be variable, but the time between a compare and jumping to the interrupt routine should be small (4 clock cycles min) depending on your timing requirements this should be ok BUT !! due to the nature of latency unless you can be sure NO OTHER INTERRUPTS CAN OCCUR DURING this process the latency is not predictable, it can vary a little. (To minimise the latency further you declare the interrupt as naked, then no context saving is employed before the interrupt is called)
 
The way you are doing it seems ok though, when the port function is overidden the port output should be set to the non compared value, ie if you set the port to clear on compare match then it should be set to 1 until the compare occurs. Again in the interrupt handler reset the values you want to set again for the next time, in this mode the pin is set before the interrupt routine is executed, therfore the action is predicatable. 
 

although i don't know your system Might PWM mode be more appropiate ?


--- In AVR-Chat@yahoogroups.com, Cat C <catalin_cluj@...> wrote:

>
> 
> Hello,
> 
> I need to generate a pulse of some length and plan to use Timer 1 on a ATMega644p in normal mode (0).
> 
> So I set 
> 
>  TCCR1A = 0b10100000; //This sets PD5/4 do be OC1A/B, to be cleared on Compare-Match
> //                ||||||||
> //                ||||||--WGM11, WGM10 (00) Normal Mode. Also set WGM13:2 in TCCRnB to 00
> //                ||||--   Reserved, must be 0
> //                ||--    COM1B1, COM1B0: 10 = Clear OC1B on Compare Match. Set at Pulse Start
> //                --       COM1A1, COM1A0: 10 = Clear OC1A on Compare Match. Set at Pulse Start
> 
>     PORTD |= _BV(PD4) | _BV(PD5);    //OC1B, OC1A as  outputs 
> 
> The plan is to set OC1A/B (PD5/4) High before I start the timer and have the timer clear them on Compare Match.
> 
> My problem is: How do I set OC1A/B to High, as they no longer "respond" to commands sent to Port D?
> I tried:
> PORTD |= _BV(PD4) | _BV(PD5); to no avail.
> 
> Any help appreciated, thanks.
> 
> Cat
>  		 	   		  
> 
> [Non-text portions of this message have been removed]
>

Hi Cat,

Yep, just got the post about forceing a compare match, i would guess thats the proper way to do it anyway lol.

Regards


--- In AVR-Chat@yahoogroups.com, Cat C <catalin_cluj@...> wrote:

>
> 
> Thanks Steven,
> That was the plan before I realized that I can have the pins changed by hardware, I think it's more repeatable.
> Anyway, maybe you missed my message that I found a way to set those pins hi.
> I don't know if PWM would be better, it seems more roundabout, I really can't tell.
> 
> Thanks again,
> 
> Cat
> 
> 
> > To: AVR-Chat@yahoogroups.com
> > From: s.holder123@...
> > Date: Wed, 7 Oct 2009 07:29:28 +0000
> > Subject: [AVR-Chat] Re: Help setting OC1A,B HI on ATMega644p, please.
> > 
> > hi.
> >  
> > >One plan could be to set the port operation as normal (COMnA1/COMnB1/
> > COMnC1 - COMnA0/COMnB0/COMnC0) to 0, set the compare interrupt bit and write an interrupt handler on compare match, when the interrupt occurs, then set the ports as desired. There will be a degree of interrupt latency especially if there are interrupts occuring, this latency will be variable, but the time between a compare and jumping to the interrupt routine should be small (4 clock cycles min) depending on your timing requirements this should be ok BUT !! due to the nature of latency unless you can be sure NO OTHER INTERRUPTS CAN OCCUR DURING this process the latency is not predictable, it can vary a little. (To minimise the latency further you declare the interrupt as naked, then no context saving is employed before the interrupt is called)
> >  
> > The way you are doing it seems ok though, when the port function is overidden the port output should be set to the non compared value, ie if you set the port to clear on compare match then it should be set to 1 until the compare occurs. Again in the interrupt handler reset the values you want to set again for the next time, in this mode the pin is set before the interrupt routine is executed, therfore the action is predicatable. 
> >  
> > 
> > although i don't know your system Might PWM mode be more appropiate ?
> > 
> > 
> 
>  		 	   		  
> 
> [Non-text portions of this message have been removed]
>

Thanks Steven,
That was the plan before I realized that I can have the pins changed by hardware, I think it's more repeatable.
Anyway, maybe you missed my message that I found a way to set those pins hi.
I don't know if PWM would be better, it seems more roundabout, I really can't tell.

Thanks again,

Cat


> To: AVR-Chat@yahoogroups.com
> From: s.holder123@btinternet.com
> Date: Wed, 7 Oct 2009 07:29:28 +0000
> Subject: [AVR-Chat] Re: Help setting OC1A,B HI on ATMega644p, please.
> 
> hi.
>  
> >One plan could be to set the port operation as normal (COMnA1/COMnB1/
> COMnC1 - COMnA0/COMnB0/COMnC0) to 0, set the compare interrupt bit and write an interrupt handler on compare match, when the interrupt occurs, then set the ports as desired. There will be a degree of interrupt latency especially if there are interrupts occuring, this latency will be variable, but the time between a compare and jumping to the interrupt routine should be small (4 clock cycles min) depending on your timing requirements this should be ok BUT !! due to the nature of latency unless you can be sure NO OTHER INTERRUPTS CAN OCCUR DURING this process the latency is not predictable, it can vary a little. (To minimise the latency further you declare the interrupt as naked, then no context saving is employed before the interrupt is called)
>  
> The way you are doing it seems ok though, when the port function is overidden the port output should be set to the non compared value, ie if you set the port to clear on compare match then it should be set to 1 until the compare occurs. Again in the interrupt handler reset the values you want to set again for the next time, in this mode the pin is set before the interrupt routine is executed, therfore the action is predicatable. 
>  
> 
> although i don't know your system Might PWM mode be more appropiate ?
> 
> 

 		 	   		  

[Non-text portions of this message have been removed]