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Setting PWM period

Setting PWM period

2011-10-11 by Philippe Habib

Thanks to all of the help I got a couple of weeks ago with timers, I have been able to get my PWM stuff (mostly) working.

I assume it is possible to tune the PWM period beyond the blunt instrument of the div by registers but I don't see how to do it.

Here are my settings, which give me a 500Hz frequency with an 8M clock.  I would like to get that to between 200 and 300 Hz if I can.  Am I missing a setting that lets me do that, or is it not possible.



	DDRD |= (1 << PD6);		// enable PWM (OC0A, PD6 ) output pin 
	OCR0A = 0;				// set PWM % 0= off 255 = full
	TCCR0A = (1 << COM0A1) | (0 << COM0A0) |  // OC0A in PWM mode
	         (0 << COM0B1) | (0 << COM0B0) |  // OC2B is not used
	         (1 << WGM01)  | (1 << WGM00);  // PWM mode
        TCCR0B = (0 << CS00) | (1 << CS01) | (0 << CS02); // div 8 on clock
	TCCR0B |= (0 << WGM02);  // more PWM mode

Thank  you.

Re: [AVR-Chat] Setting PWM period

2011-10-11 by Jim Wagner

On Oct 10, 2011, at 8:34 PM, Philippe Habib wrote:

> Thanks to all of the help I got a couple of weeks ago with timers, I  
> have been able to get my PWM stuff (mostly) working.
>
> I assume it is possible to tune the PWM period beyond the blunt  
> instrument of the div by registers but I don't see how to do it.
>
> Here are my settings, which give me a 500Hz frequency with an 8M  
> clock. I would like to get that to between 200 and 300 Hz if I can.  
> Am I missing a setting that lets me do that, or is it not possible.
>
> DDRD |= (1 << PD6);	 // enable PWM (OC0A, PD6 ) output pin
> OCR0A = 0;	 // set PWM % 0= off 255 = full
> TCCR0A = (1 << COM0A1) | (0 << COM0A0) | // OC0A in PWM mode
> (0 << COM0B1) | (0 << COM0B0) | // OC2B is not used
> (1 << WGM01) | (1 << WGM00); // PWM mode
> TCCR0B = (0 << CS00) | (1 << CS01) | (0 << CS02); // div 8 on clock
> TCCR0B |= (0 << WGM02); // more PWM mode
>
> Thank you.
> 
There are modes where the timer resets based on the value in one  
compare register or, perhaps, the capture register. Most of these  
timers have two compare registers. This allows you to use one to set  
the period and the other to set the PWM time.

Jim Wagner
Oregon Research Electronics

[Non-text portions of this message have been removed]

Re: [AVR-Chat] Setting PWM period

2011-10-11 by Clark Martin

On Oct 10, 2011, at 8:34 PM, Philippe Habib wrote:

It would help if you listed the processor in use.  Without that we can't know what the settings mean.

> Thanks to all of the help I got a couple of weeks ago with timers, I have been able to get my PWM stuff (mostly) working.
> 
> I assume it is possible to tune the PWM period beyond the blunt instrument of the div by registers but I don't see how to do it.
> 
> Here are my settings, which give me a 500Hz frequency with an 8M clock. I would like to get that to between 200 and 300 Hz if I can. Am I missing a setting that lets me do that, or is it not possible.
> 
> DDRD |= (1 << PD6);	 // enable PWM (OC0A, PD6 ) output pin 
> OCR0A = 0;	 // set PWM % 0= off 255 = full
> TCCR0A = (1 << COM0A1) | (0 << COM0A0) | // OC0A in PWM mode
> (0 << COM0B1) | (0 << COM0B0) | // OC2B is not used
> (1 << WGM01) | (1 << WGM00); // PWM mode
> TCCR0B = (0 << CS00) | (1 << CS01) | (0 << CS02); // div 8 on clock
> TCCR0B |= (0 << WGM02); // more PWM mode

Clark Martin
Redwood City, CA, USA
Macintosh / Internet Consulting

"I'm a designated driver on the Information Super Highway"



[Non-text portions of this message have been removed]

Re: [AVR-Chat] Setting PWM period

2011-10-11 by Clark Martin

On Oct 10, 2011, at 9:11 PM, Jim Wagner wrote:

> 
> On Oct 10, 2011, at 8:34 PM, Philippe Habib wrote:
> 
>> Thanks to all of the help I got a couple of weeks ago with timers, I  
>> have been able to get my PWM stuff (mostly) working.
>> 
>> I assume it is possible to tune the PWM period beyond the blunt  
>> instrument of the div by registers but I don't see how to do it.
>> 
>> Here are my settings, which give me a 500Hz frequency with an 8M  
>> clock. I would like to get that to between 200 and 300 Hz if I can.  
>> Am I missing a setting that lets me do that, or is it not possible.
>> 
>> DDRD |= (1 << PD6);	 // enable PWM (OC0A, PD6 ) output pin
>> OCR0A = 0;	 // set PWM % 0= off 255 = full
>> TCCR0A = (1 << COM0A1) | (0 << COM0A0) | // OC0A in PWM mode
>> (0 << COM0B1) | (0 << COM0B0) | // OC2B is not used
>> (1 << WGM01) | (1 << WGM00); // PWM mode
>> TCCR0B = (0 << CS00) | (1 << CS01) | (0 << CS02); // div 8 on clock
>> TCCR0B |= (0 << WGM02); // more PWM mode
>> 
>> Thank you.
>> 
> There are modes where the timer resets based on the value in one  
> compare register or, perhaps, the capture register. Most of these  
> timers have two compare registers. This allows you to use one to set  
> the period and the other to set the PWM time.

For the Mega 328 it looks like you get this mode with WGM02 = 1. I've never used this mode (I think I will though.  Note that this means the PWM value will vary from 0 - OCR0A or in this case, 0 - 100 to 125 roughly.

Clark Martin
Redwood City, CA, USA
Macintosh / Internet Consulting

"I'm a designated driver on the Information Super Highway"

Re: [AVR-Chat] Setting PWM period

2011-10-11 by Philippe Habib

Sorry, I'm using at ATMEGA48.
Show quoted textHide quoted text
----- Original Message -----
From: "Clark Martin" <cmmac@sonic.net>
To: AVR-Chat@yahoogroups.com
Sent: Monday, October 10, 2011 9:15:56 PM
Subject: Re: [AVR-Chat] Setting PWM period


On Oct 10, 2011, at 8:34 PM, Philippe Habib wrote:

It would help if you listed the processor in use.  Without that we can't know what the settings mean.

> Thanks to all of the help I got a couple of weeks ago with timers, I have been able to get my PWM stuff (mostly) working.
> 
> I assume it is possible to tune the PWM period beyond the blunt instrument of the div by registers but I don't see how to do it.
> 
> Here are my settings, which give me a 500Hz frequency with an 8M clock. I would like to get that to between 200 and 300 Hz if I can. Am I missing a setting that lets me do that, or is it not possible.
> 
> DDRD |= (1 << PD6);	 // enable PWM (OC0A, PD6 ) output pin 
> OCR0A = 0;	 // set PWM % 0= off 255 = full
> TCCR0A = (1 << COM0A1) | (0 << COM0A0) | // OC0A in PWM mode
> (0 << COM0B1) | (0 << COM0B0) | // OC2B is not used
> (1 << WGM01) | (1 << WGM00); // PWM mode
> TCCR0B = (0 << CS00) | (1 << CS01) | (0 << CS02); // div 8 on clock
> TCCR0B |= (0 << WGM02); // more PWM mode

Clark Martin
Redwood City, CA, USA
Macintosh / Internet Consulting

"I'm a designated driver on the Information Super Highway"



[Non-text portions of this message have been removed]



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