AVR-Chat

Greetings,

I am designing an tiny13 based voltage monitor.  I wish to use the
internal reference to measure input voltages up to 15V, thus I need a
voltage divider at the A/D input.  I wish to reduce power consumption to
a minimum.  What minimum current through the divider would provide a
reasonably stiff voltage at the A/D pin?

A suggestion where to find such documentation, or an informed guess
welcome.

Stu

On Apr 2, 2012, at 8:32 PM, stu_ki6j wrote:

> I am designing an tiny13 based voltage monitor. I wish to use the
> internal reference to measure input voltages up to 15V, thus I need a
> voltage divider at the A/D input. I wish to reduce power consumption to
> a minimum. What minimum current through the divider would provide a
> reasonably stiff voltage at the A/D pin?
> 
> A suggestion where to find such documentation, or an informed guess
> welcome.


I don't know about the 13 but for the ATtiny85, in the section titled Analog Input Circuitry is this line:

    "The ADC is optimized for analog signals with an output impedance of approximately 10 kΩ or less."

So the voltage divider needs an impedance of 10K ohms or less.  If it's your basic two resistor voltage divider this means the resistors if in parallel need to be less than 10K. 


 ie. 10K >= 1 / (1 / R1 + 1 / R2)

That is assuming the source impedance of the monitored voltage is very low, otherwise you need to add it to the resistance of the high side of the divider.




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From the datasheet, the recommendation is for the source impedance to be 10K or less as there is a sample and hold circuit inside that can give incorrect readings if not charged sufficiently quickly between samples. 
The sample time can be adjusted in the registers (by reducing the A/D clock time) If you have a spare pin you could use that to turn on a transistor while you do the measurement then turn it off so that there is no current flow when not measuring. 
For low current appliactions it is not generally a good idea just to hace a potential divider as the current is always there no matter what you are doing (it's a waste) I have used resistances up 1Meg before but had to slow the sample time down and take multiple samples to get a pattern rather than a spot measurement, in a battery application this is preferrable than having the constant current draw.
 
Regards
 


________________________________

From: stu_ki6j <ki6mwn@yahoo.com>
To: AVR-Chat@yahoogroups.com 
Sent: Tuesday, 3 April 2012, 4:32
Subject: [AVR-Chat] A/D current requirements


  

Greetings,

I am designing an tiny13 based voltage monitor. I wish to use the
internal reference to measure input voltages up to 15V, thus I need a
voltage divider at the A/D input. I wish to reduce power consumption to
a minimum. What minimum current through the divider would provide a
reasonably stiff voltage at the A/D pin?

A suggestion where to find such documentation, or an informed guess
welcome.

Stu




[Non-text portions of this message have been removed]

On Tue, 3 Apr 2012 11:32:01 stu_ki6j wrote:

> I am designing an tiny13 based voltage monitor.  I wish to use the
> internal reference to measure input voltages up to 15V, thus I
> need a voltage divider at the A/D input.  I wish to reduce power
> consumption to a minimum.  What minimum current through the
> divider would provide a reasonably stiff voltage at the A/D pin?

> A suggestion where to find such documentation, or an informed guess
> welcome.

Data Sheet. Table 18.7 puts the input impedance at 100 MOhm

Keep your external divider impedance a decade lower.

If the working range of battery voltages is much smaller than the
peak voltage (e.g. 8V to 15V), then you can expand the useful
resolution of measurement by having the tiny13 "float" above the
battery negative slightly below that higher, minimum voltage.

One way of minimising the parasitic loss due to the voltage monitor
is to put a FET in the voltage divider and switch that on using one
of the tiny13's digital outputs when you want to take a measurement.
Check the specs of the FET for its impedance when "off".

-- 
/"\ Bernd Felsche - Innovative Reckoning, Perth, Western Australia
\ /  ASCII ribbon campaign | For every complex problem there is an
 X   against HTML mail     | answer that is clear, simple, and wrong.
/ \  and postings          |  --HL Mencken

Thank you, gentlemen.

I was afraid the information was hiding in the datasheet despite my search.  Yes, Table 18-7 is included in my copy as well.

A 10 Mohm divider indicated would put my standing current at a tolerable 1.x uA.  I like the idea of a FET switch to turn the divider "on"; I have a pin and code space to spare.  I do want to keep the circuit simple as well.

I am including a calibration routine to set response thresholds (2 led status indicators), so I have convinced myself that variations of the internal reference voltage from chip to chip shouldn't matter.  If however, internal Vref is influenced greatly by environment, I may have to rethink that point.

I also like the idea of "floating" the ground of the monitor circuit, compressing the readable range and giving better resolution.  I am only a hobbyist, so I have to put some thought into the implications of presenting a voltage below Vgnd to the A/D pin, even with the chip un-powered.

I plan to average four conversion values (easy math) before comparing with the calibration values in EEPROM.  Slow is fine for this application.  Is this method ill advised?

Thanks again for the warm welcome.

Stu

On Apr 3, 2012, at 5:10 PM, stu_ki6j wrote:

> Thank you, gentlemen.
> 
> I was afraid the information was hiding in the datasheet despite my search. Yes, Table 18-7 is included in my copy as well.
> 
> A 10 Mohm divider indicated would put my standing current at a tolerable 1.x uA. I like the idea of a FET switch to turn the divider "on"; I have a pin and code space to spare. I do want to keep the circuit simple as well.
> 
> I am including a calibration routine to set response thresholds (2 led status indicators), so I have convinced myself that variations of the internal reference voltage from chip to chip shouldn't matter. If however, internal Vref is influenced greatly by environment, I may have to rethink that point.
> 
> I also like the idea of "floating" the ground of the monitor circuit, compressing the readable range and giving better resolution. I am only a hobbyist, so I have to put some thought into the implications of presenting a voltage below Vgnd to the A/D pin, even with the chip un-powered.
> 
> I plan to average four conversion values (easy math) before comparing with the calibration values in EEPROM. Slow is fine for this application. Is this method ill advised?
> 
> Thanks again for the warm welcome.

For one thing, before you try switching the input on and off, figure out just how much current you are drawing to monitor the voltage and compare it with other sleep loads.  It may turn out to be inconsequential.  Also, experiment, learn...  With an adequate capacitor how high of resistance can you get a away with in the divider circuit?  What is the sleep current of everything?  The voltage you are monitoring, what is it doing when the processor is sleeping?

Perhaps if you described your situation in more detail we might have some ideas for you.



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