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Re: Atompro timing anomolies....

2007-01-20 by djbrow54

I coded up two approaches to module synchronization.

Alt 1:  I setup the PSIM as the master clock using 1 mS timer 
interrupts.  I sent a $fe midi active sense every mS to the other 
module.  I generated the real-time clock in the other module on 
receipt of the midi active sense instead of the timer.  Latency 
between the two was ~400 uS which is what I would expect given 
transmission time and interrupt latency. 

Alt 2:  I setup both modules using 1 mS timer interrupts.  I sent a 
$fe midi active sense every 256 mS to synchronize the two clocks.  I 
output a periodic 1 mS clock and there is some minor jitter but the 
modules stay synchronized.  I put a .wmv video in the 
Files>BasicAtomPro>Original PSIM>Dave Brown folder showing the 
results.

In both cases I would need to add some code for specific 
synchronization due to reset and start-up time differences between 
modules.  In  alternative 1 I would just pause long enough to make 
sure the interrupts were enabled.  In alternative 2 I would probably 
add code for a midi reset to reset the real-time clock value.

Dave


--- In ComputerVoltageSources@yahoogroups.com, "djbrow54" <davebr@...> 
wrote:
>
> I would take a much simpler approach.  You don't have to follow the 
> MIDI standard.  Whatever code I wrote would rely upon the timer for 
> some standard timing increment.  I do all of my code with a 1 mS 
> timer.  If you ignore the accuracy and assume the resonator is good 
> enough (mine is 0.1% accurate), I would simply declare one processor 
> to be a master, and during the ISR I would send a timing code out 
via 
> serial/MIDI.  You can pick whatever code you want as long as it is 
> unused by your application.  The other PSIMs do not use a timer 
> routine, but rather implement received serial via interrupts.  That 
> particular code replaces the timer interrupt and is filtered from 
the 
> MIDI stream (if you're even using MIDI).  There is some latency.  At 
> MIDI rates, it would be 320 uS.  Figure out what the latency is and 
> add it to the master with a software delay.  I figure you can keep 
all 
> of these sync'd  with some relative timing offset but good overall 
> accuracy.  You don't have to do the 24 ppq but can run on a much 
> higher rate.  The idea is to keep the processors from drifting apart 
> over long time intervals.  The solution is to only use one timing 
> reference.
> 
> The other option would be to use an external clock via Aux.  You can 
> set up Aux for edge interrupts.  The master timer ISR pulses Aux.  
The 
> slaves setup Aux for edge interrupts  Latency is much lower but 
> consume one I/O pin.
> 
> Dave

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