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question about quad adsr

question about quad adsr

2008-02-07 by Carlos

I got this module yesterday and is quite everything I expected. Great
to get the eg's auto triggering each other and create interesting
patterns.

Question though, how come to get each of the adsr to constantly
re-trigger itself it has to be patched to 'end of decay'? I thought it
would work at 'end of release' since thats the last part of the
envelope no? 

yet it doesn't work when I patch it that way. yet when I patch it to
end of decay I still seem to to get both the sustain (expected) and
release (unexpected) portions of the envelope on the output.

Re: question about quad adsr

2008-02-07 by Carlos

Ok that explains why patching to end of release wouldn't work as
expected, 

but how come then that patching with 'end of decay' I still seem to
get the release of the envelope on every repeat? not complaining thats
the behavior I want, but just wondering

Carlos


--- In Doepfer_a100@yahoogroups.com, <hardware@...> wrote:
>
> > I got this module yesterday and is quite everything I expected. Great
> > to get the eg's auto triggering each other and create interesting
> > patterns.
> >
> > Question though, how come to get each of the adsr to constantly
> > re-trigger itself it has to be patched to 'end of decay'? I thought it
> > would work at 'end of release' since thats the last part of the
> > envelope no?
> 
> I remember that we had the same "problem" in the company during the
> development of the A-143-2. Let me try to explain it:
> The 'end of release' output is generated by a comparator that
compares the
> ADSR output to a small voltage (about 100mV). As soon as the ADSR output
> becomes lower than this voltage the 'end of release' output turns
'high'.
> And the other way round: as soon as the ADSR output becomes higher
than this
> voltage the 'end of release' output turns back to low level.
> 
> If the 'end of release' output is connected to the gate input this
happens:
> As soon as the ADSR output becomes lower than about 100mV the gate turns
> high and the attack phase begins for a very short time. This time is
very
> short because now the ADSR output voltage increases and reaches the
100mV
> very soon (probably less than a millisecond) which causes the 'end of
> release' output to turn low which immediately ends the attack phase.
With an
> oscilloscope you would see a signal that swings very fast around the
100mV
> threshold level of the 'end of release' circuit.
> 
> If you want to use the 'end of release' output to trigger the gate
you need
> a circuit that elongates the length of the 'end of release' signal. For
> example the A-162 trigger delay (with Delay = Zero) can do this job. The
> length of the A-162 defines how long the signal remains high. This time
> corresponds to the setting of the attack control of the A-143-2.
> 
> I know the explanation is very technical but I hope you will
understand the
Show quoted textHide quoted text
> behaviour of this patch.
> 
> Best wishes
> Dieter Doepfer
>

AW: [Doepfer_a100] question about quad adsr

2008-02-07 by hardware@doepfer.de

> I got this module yesterday and is quite everything I expected. Great
> to get the eg's auto triggering each other and create interesting
> patterns.
>
> Question though, how come to get each of the adsr to constantly
> re-trigger itself it has to be patched to 'end of decay'? I thought it
> would work at 'end of release' since thats the last part of the
> envelope no?

I remember that we had the same "problem" in the company during the
development of the A-143-2. Let me try to explain it:
The 'end of release' output is generated by a comparator that compares the
ADSR output to a small voltage (about 100mV). As soon as the ADSR output
becomes lower than this voltage the 'end of release' output turns 'high'.
And the other way round: as soon as the ADSR output becomes higher than this
voltage the 'end of release' output turns back to low level.

If the 'end of release' output is connected to the gate input this happens:
As soon as the ADSR output becomes lower than about 100mV the gate turns
high and the attack phase begins for a very short time. This time is very
short because now the ADSR output voltage increases and reaches the 100mV
very soon (probably less than a millisecond) which causes the 'end of
release' output to turn low which immediately ends the attack phase. With an
oscilloscope you would see a signal that swings very fast around the 100mV
threshold level of the 'end of release' circuit.

If you want to use the 'end of release' output to trigger the gate you need
a circuit that elongates the length of the 'end of release' signal. For
example the A-162 trigger delay (with Delay = Zero) can do this job. The
length of the A-162 defines how long the signal remains high. This time
corresponds to the setting of the attack control of the A-143-2.

I know the explanation is very technical but I hope you will understand the
behaviour of this patch.

Best wishes
Dieter Doepfer

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