Apple Logic Pro /LogicExpress Discussion

> I think all modern CPUs are "pipeline" machines. A command 
> doesn't just execute. It goes through 10 or 12 stages, so at 
> any given time 10 or 12 instructions are being processed. A 
> memory call can be made on the first cycle and read on the 
> 4th so its not a waste of time. 

Yes. Absolutely, and your described situation can occur. However, the
pipeline in no ways *ensures* that will be the case. It only makes it much
more likely. There can be code dependencies that prevent it. In other words.
Even though the CPU is capable of performing several pipelined operations
after requesting a particular byte of memory. If the results of that memory
must be available for the currently pipelined code to go on to the next
instruction, the pipeline is potentially held up.

I'm definitely not a CPU expert, and not a pipeline architecture expert by
any means either. However, I think I can safely say that if two independent
CPUs are trying to access the same memory and that memory is running on a
slower bus, it is ultimately going to be a bottle neck. There are modern CPU
tricks that reduce the effects of the bottle neck, as you have pointed out,
but you simply can't get rid of it altogether.

Kamm