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Analog Shift Register experiment

Analog Shift Register experiment

2009-03-13 by johnrichoux

Hi all
I'm not sure how I got started on this, but I can't help but wonder if what I am trying to do with ASR's is actually possible: to loop the memories and keep them stable. In other words, to keep the same 3 values playing in a switchable loop. I've used 2 ASR's in order to try to vary or lag the pulse time. I do get a looping but it gradually but invariably resamples slightly lower until everything is zero. (Not that this in itself is a bad thing)

The goal is to have the contents change whenever TKB KP is detected, but when it isn't, to have a clock cycle thru and repeat and hold the contents until the next KP. I use the ACPR & BLOG to control the routing.

I have assumed that the problem is the ASR needs more time to resample.

Any ideas?

Thanks
jmr

Analog Shift Register experiment

2009-03-14 by sasami@hotkey.net.au

The ASR loads through a ripple effect. Last stage is loaded with middle
stage voltage, THEN middle stage is loaded with first stage, THEN first
stage samples new content. With two ASRs you have six steps in this ripple
effect. Something to consider with your patch.
Show quoted textHide quoted text
>Hi all
>I'm not sure how I got started on this, but I can't help but wonder if
what I am trying to do with ASR's is actually possible: to loop the memories
and keep them stable. In other words, to keep the same 3 values playing in a
switchable loop. I've used 2 ASR's in order to try to vary or lag the pulse
time. I do get a looping but it gradually but invariably resamples slightly
lower until everything is zero. (Not that this in itself is a bad thing)
>
>The goal is to have the contents change whenever TKB KP is detected, but
when it isn't, to have a clock cycle thru and repeat and hold the contents
until the next KP. I use the ACPR & BLOG to control the routing.
>
>I have assumed that the problem is the ASR needs more time to resample.
>
>Any ideas?
>
>Thanks
>jmr
>
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