Richard Brewster
http://pugix.com
On 6/18/15 6:40 PM, Ken Stone otherunicorn@... [cgs_synth] wrote:
It may have more to do with the speed of the clock chip. Try adding a 1M between pins 7 and 5 of the TL072 that is used to process the clock signal.
On Fri, Jun 19, 2015 at 4:37 AM, spunraddish@... [cgs_synth] <cgs_synth@yahoogroups.com> wrote:
Nope, did that and did a few more mods, to no effect - in loop mode there are only 4 eventualities - no steps on, 3 steps on, two steps on with a space between them, and 7 steps on. When not in loop mode, it seems there may be a sort of logic to when step 6-8 stay on and off, as I've obtained mostly rhythmic patterns that repeat after 3-4 cycles, not without error though. Faster patterns have less errors outside of loop mode. In loop mode, when I lose all steps, it's a relatively slow clock and they disappear around step 4. When it organizes to the other two patterns, it is a quicker rate.
Perhaps it has something to do with the 1n cap value?
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