The only "issue" having the reset cap to big is that it may prevent a clock pulse from advancing close to when the reset occurred.
On Sun, Jun 25, 2017 at 6:42 PM, Paul Bower paul@... [cgs_synth] <cgs_synth@yahoogroups.com> wrote:Good to hear from you Ken - hope things are good over thereSince that’s all I had, I just put a 47nF cap across the existing 10nF and that did the trickIn case anyone else comes across this, it was a very old board. I could get the gate sequencer to reset from its own 12V step outputs, but not from an LFO that was sending a 0-8.5V squarewave (and certainly not from a variety of things I tried at around the 5V mark)So all fixed - I can reset on a 4.5V pulse nowI assume that if I get misfiring problems now then I just need to reduce the value of that bridging cap a little ?CheersPaulOn 25 Jun 2017, at 02:21, Ken Stone otherunicorn@... [cgs_synth] <cgs_synth@yahoogroups.com> wrote:I should work that way already. Perhaps increase the size of the 10n reset cap to 47n to let a bigger pulse through.
On Sun, Jun 25, 2017 at 6:44 AM, Paul Bower paul@... [cgs_synth] <cgs_synth@ yahoogroups.com> wrote:Hello there,
Just wondering if anyone could recommend a way of modding the reset input to accept +5V instead of +12/13VCheersPaul
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