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Re: Unreliable Secondary JTAG Connection

2005-11-09 by bruce_p1

I was searching through this group to see if anyone else was having 
an unreliable secondary JTAG connection issue with the LPC210x 
chips; guess I'm not alone.

I too am using a Nohau JTAG debugger; the EMUL-ARM, but that doesn't 
seem to be the issue.

According to the LPC210x datasheet, to enable secondary JTAG you 
have to bring DBGSEL or RTCK low to disable primary JTAG pins and 
ETM, then setup the secondary pins in software.  My original setup 
was RTCK high and DBGSEL low.  It worked perfectly on some boards, 
but not on my current board.  Then I tried both pins low with the 
same results.

After much searching through groups and sites, I found a note from 
an LPC user that said he had pulled DBGSEL high and RTCK low to fix 
random LPC210x chips that wouldn't go into secondary JTAG.

This worked perfectly and I could recreate the scenario every time!

I have a question into Philips as to what the real deal is and why 
this works.  I was wondering if it was a reset or power sequencing 
issue since I have other boards that don't do this.  Since all the 
signals are internal to the chip, it sure seems like an issue on 
random LPC210x chips.

Regardless, I thought I'd pass this along since it seemed to be a 
hot topic a while back.

Comments or similar experiences?

Regards,

Bruce


--- In lpc2000@yahoogroups.com, "James Dabbs" <jdabbs@t...> wrote:
>
> I am using a Nohau JTAG ICE connected to the second port on a 
LPC2106.
> The emulator does not make a reliable connection to the JTAG unit 
on the
> chip.
> 
> On my design, I have DBGSEL pulled to ground.  Right after reset, I
> execute the following code segment:
> 
>   ldr  r0,=0x55400000
>   ldr  r1,=0xE002C004
>   str  r0,[r1]
> 
> On my board, I connect the 20-pin JTAG header to the LPC2106 like 
this:
> 
>   NTRST (3)	-> P0.27/TRC0/TRST (8)
>   TDI (5)	-> P0.30/TRC3/TDI  (15)
>   TMS (7)	-> P0.28/TRC1/TMS (9)
>   TCK (9)	-> P0.29/TRC2/TCK (10)
>   RTCK (11)	-> RTCK (26)
>   TDO (13)	-> P0.31/EXTIN0/TDO (16)
>   NRST (15)	-> RST (5)
> 
> Right after enabling the secondary JTAG port, I have a code loop 
that
> toggles an I/O pin.  I can see this happening, and then when I run 
the
> emulator, the toggling stops.  It doesn't reset; it just pauses
> execution.  I know this because the I/O pin doesn't go back to 
being an
> input.  However, the JTAG emulator is unable to "enter a debug 
state"
> which means it can't talk to the JTAG interface on the chip.  
Every once
> in a while (twice, so far) it connects and I can debug my S/W, but 
99.9%
> of the time it does not.
> 
> This is essentially the same design as a different project I used 
last
> year, but I am having trouble with it now.
> 
> Am I breaking some rule here?  Is there anything obvious in what I 
am
> doing that could cause this?
> 
> Thanks.
>

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