Tom, What you describe is the norm for secondary JTAG debugging and is well understood. But, some people, including myself, have seen this not work on some LPC chips on certain circuit boards. The only way I saw it fixed was to keep DBGSEL high and RTCK low. I have designed quite a few other boards that work perfectly, but have now seen random chips not allowing a secondary JTAG connection. This makes me wonder if there is a certain combination of things that cause this issue (e.g., on-board capacitance, certain batches of chips from a certain fab, reset timing, crystal frequency, power supply sequencing, timing issue with DBGSEL, etc.). These things can probably only be answered by the Philips designers is my guess. Regards, Bruce --- In lpc2000@yahoogroups.com, Tom Walsh <tom@o...> wrote: > > bruce_p1 wrote: > > >I was searching through this group to see if anyone else was having > >an unreliable secondary JTAG connection issue with the LPC210x > >chips; guess I'm not alone. > > > >I too am using a Nohau JTAG debugger; the EMUL-ARM, but that doesn't > >seem to be the issue. > > > >According to the LPC210x datasheet, to enable secondary JTAG you > >have to bring DBGSEL or RTCK low to disable primary JTAG pins and > >ETM, then setup the secondary pins in software. My original setup > >was RTCK high and DBGSEL low. It worked perfectly on some boards, > >but not on my current board. Then I tried both pins low with the > >same results. > > > >After much searching through groups and sites, I found a note from > >an LPC user that said he had pulled DBGSEL high and RTCK low to fix > >random LPC210x chips that wouldn't go into secondary JTAG. > > > >This worked perfectly and I could recreate the scenario every time! > > > >I have a question into Philips as to what the real deal is and why > >this works. I was wondering if it was a reset or power sequencing > >issue since I have other boards that don't do this. Since all the > >signals are internal to the chip, it sure seems like an issue on > >random LPC210x chips. > > > >Regardless, I thought I'd pass this along since it seemed to be a > >hot topic a while back. > > > > > > > > This is a Rev 0 board that I'm building, so far one-of-a-kind (until > production). I tie both DEBUG + RTCK low through 10K resistors. Then, > I put this in crt0.S: > > ======= begin ============ > start: > _start: > _mainCRTStartup: > ldr r0, JTAG2 > ldr r1, PINSELREG > str r0, [r1] > ; > ========= snip ========== > > Variables are defined as: > > ========= begin ========= > JTAG2: > .word 0x55400000 > PINSELREG: > .word 0xe002c004 > ========== snip ========= > > So far, no problems with JTAG. I'm daisy chaining with an LPC2138 that > is first in the chain. > > TomW > > -- > Tom Walsh - WN3L - Embedded Systems Consultant > http://openhardware.net, http://cyberiansoftware.com > "Windows? No thanks, I have work to do..." > ---------------------------------------------------- >
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Re: Unreliable Secondary JTAG Connection
2005-11-09 by bruce_p1
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