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Re: [lpc2000] shared memory between processors

2005-11-21 by David Hawkins

Doug Sutherland wrote:
> Sorry if this is a dumb question: regarding shared memory between
> processors, if I have 2 ARM processors both with memory expansion,
> can they be connected together directly on the EMI, or do I need
> some buffer hardware in between? Wondering also about the same
> thing for a DSP with memory expansion (TI Parallel Host Interface) 
> connecting to ARM, direct connect is okay? I'm assuming direct
> connect only if the chip specs indicate allowable voltage tolerance.

Hey Doug,

I have not used an LPC with an external memory interface,
but I'll suggest a few things.

If you wanted to connect two ARM processors together, then
the one reading/writing would be the Master of the interconnected
bus, while the other would be the slave. So, check if the
LPC EMI supports a slave connection. If not, then you'll
need a bit of logic between the two. I'm a fan of interfacing
to FPGAs, eg. the Altera FLEX or Cyclone FPGAs are fairly
cheap (<$20 for a fairly dense device), and Xilinx has their
Spartan series. Both Altera and Xilinx have free web tools,
so cost of development with FPGAs is usually due to the
learning curve of VHDL or Verilog. I'll help with VHDL if
thats the way you want to go.

The TI HPI interface can be operated in 16-bit or 8-bit mode
if I recall correctly. There is a good chance you could
connect the ARM to this port as a Master, making it read
or write to the DSP registers, but if the ARM cannot
be configured in a slave mode, then it won't work the
other way.

Even with the FPGA approach, you won't get the ARM into
a slave mode if it does not exist. However, you can use
an FPGA between two LPC devices to create a FIFO or
shared memory area, that each ARM device can write
to or read from, and an interrupt can be used to
synchronize access.

Of course, depending on the data rate required, connecting
two devices using SPI, I2C, or UART might be simpler.
This applies to the ARM-DSP connection too.

Dave

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