Lpc2000

Oops,

I meant to state that if TDI is valid on a rising edge of TCK and you 
read TDO on the falling edge you may not need RTCK.
If your TCK is slow enough (1/6 of CCLK) you can do without RTCK (TCK 
should be <  1/6 CCLK).

RTCK is especially usefull if you have large variations in the CPU clock 
(CCLK) or if you have a low CCLK and want to use the highest possible TCK.

Rob

householder_lpc wrote:

>So if you need the RTCK, you cannot use the wiggler interface, as it
>doesn't support RTCK? 
>
>--- In lpc2000@yahoogroups.com, Rob Jansen <rob@m...> wrote:
>  
>
>
>>Reason for a number of JTAG debugger pods not to work with the -S 
>>variant is the RTCK signal. This is highly depending on the internal 
>>clocking of signals inside the JTAG pod and the clock frequency used.
>>The internal clock signal (DBGTCKEN) that is connected to the ARM core 
>>has a delay of 3 CLK (ARM core clock) cycles from the TCK input. TDI is 
>>sampled at DBGTCKEN and TDO is generated using that same internal clock.
>>This means that if you have a hardware interface that samples the TDO 
>>signal at a TCK positive edge you miss the signal (it's only valid just 
>>a bit later).
>>
>>According to the JTAG spec (at least the timing diagrams I have seen) 
>>the TDO signal is still valid at the falling edge of TCK. So if you 
>>would design your JTAG POD with this in mind, you will not miss the TDO 
>>signal.
>>The only thing to remember is that debugging a system with clock
>>    
>>
>control 
>  
>
>>(I've used a system that could work on either 32 kHz or a 13 MHz clock) 
>>will mean that you have to change your JTAG CLK frequency. Using the 
>>RTCK makes sure you always keep running in sync with the ARM core.
>>    
>>