Lpc2000

Hello,

On Saturday 31 December 2005 17:31, deliconn wrote:
> Sorry if this question has been addressed before.  I searched through
> the messages and didnt see anything.  I have decided that I dislike
> the yahoo group design.
>
Yes.

> I just started using the LPC2148 for its fast I/O.  And so far I have
> not been disappointed.  But I have really only been outputting at high
> speeds.  My design now, requires the ARM to react to an outside event
> and I only have ~850ns from the time my indication goes high to when
> it goes low.  All my work needs to get done in that tiny space.
>
> So I hooked my external indication to an input pin.  I set up my
> FIOMASK so only that pin is visible and I hand assembled the tightest
> loop possible.  The C equivalent is:
>   while(1) {
>       if(FIOPIN) {
>           FIOSET = my signal pin
>           FIOCLR = my signal pin
>       }
>   }
>
> What I found using a logic analyzer, sampling at 500MHz, is that the
> time between my external indication going high and the time my signal
> pin goes high is about ~230ns.  I am running my ARM at 58.9MHz (I will
> be changing to 60MHz when parts get in).  I realize that a couple
> clock cycles get wasted raising my signal pin and a couple may get
> lost if I am in the 'while' jump, but why is it taking so long to
> register the external input?  Does using the mask register carry any
> overhead, seems silly if it did?
>
> What is the fastest number of clocks the ARM can recognize that there
> is input?
>
I don't think your 230ns are too bad. At 58.9 MHz you have 16.98ns per cycle.
The smallest loop I could come up with looks like this:

loop:
ldr r0, [FIOPIN] (reg holding address of IOPIN)
tst r0, MASK
strne OUTMASK, [FIOSET] (reg holding address of IOSET)
strne OUTMASK, [FIOCLR] (reg holding address of IOSET)
b loop

A load requires at least 3 cycles, the test 1 cycle and the store 2 cycles. 6 
cycles or ~102ns are the absolute minimum. If the store's condition isn't 
fulfilled, it takes 1 cycle, and the branch takes 3 cycles.
If the input isn't high in time for the ldr, up to 14 cycles or ~238ns are 
going to pass. These are optimum values, where no additional delay beyond 
that of the ARM7TDMI-S instruction cycle timing occurs. What does your 
assembly look like, and does the code run from single-cycle memory?

> Oh, one more thing, I was initially going use an external interrupt
> FIQ before I learned of my ~850ns window.  So the initial design has
> the external indication coming in on P0.15.  I havent tried using a
> different input pin yet.  I only mention it because there may be some
> type of overhead when using a pin that could also be set as an
> external interrupt.
>
> Thanks for any help,
>
> Vern

Kind regards,

Dominic