Lpc2000

Hi Dominic,

Thanks for taking the time to reply.

> I don't think your 230ns are too bad. At 58.9 MHz
> you have 16.98ns per cycle.
> The smallest loop I could come up with looks like
> this:
> 
> loop:
> ldr r0, [FIOPIN] (reg holding address of IOPIN)
> tst r0, MASK
> strne OUTMASK, [FIOSET] (reg holding address of
> IOSET)
> strne OUTMASK, [FIOCLR] (reg holding address of
> IOSET)
> b loop
> 
> A load requires at least 3 cycles, the test 1 cycle
> and the store 2 cycles. 6 
> cycles or ~102ns are the absolute minimum. If the
> store's condition isn't 
> fulfilled, it takes 1 cycle, and the branch takes 3
> cycles.
> If the input isn't high in time for the ldr, up to
> 14 cycles or ~238ns are 
> going to pass. These are optimum values, where no
> additional delay beyond 
> that of the ARM7TDMI-S instruction cycle timing
> occurs. What does your 
> assembly look like, and does the code run from
> single-cycle memory?

I am running my code from the internal SRAM on the
LPC2148.  My assembly is the same as yours.  I have
preloaded registers with values and addresses before I
enter my loop, just like you have. 

I think that a redesign may be in order.  Anyone know
a good 250MHz ARM7 with local SRAM.  Just kidding.

Thanks again.

Vern



		
__________________________________________ 
Yahoo! DSL \ufffd Something to write home about. 
Just $16.99/mo. or less. 
dsl.yahoo.com