Lpc2000

> -----Original Message-----
> From: lpc2000@yahoogroups.com [mailto:lpc2000@yahoogroups.com] On Behalf
> Of itsjustimpossible
> Sent: Tuesday, January 10, 2006 6:33 AM
> To: lpc2000@yahoogroups.com
> Subject: [lpc2000] Interfacing FPGA to lpc2294 external bus
> 
> Hi
> I need to interface an FPGA to the external bus of the LPC2294 so
> that I can directly read and write to the BlockRam internal to the
> FPGA (Arranged as a dual-port RAM).
> 
> I just wondered if someone has already achieved this or knows of
> some example VHDL they can point me at. We are very new to this,
> just attended a VHDL course, and am wondering about the correct way
> to go about it.
> 
> The XCLK seems to be the key to this, but I am currently trying to
> sort out how to handle the control lines and the tri-state buffers.
> 
> The statement in the data sheet that is causing me a problem is
> the "CS and OE lines may become low one XCLK earlier than is shown".
> I assume then that I cannot use these lines directly as the address
> bus may not be stable at that point.
> 
> I know this is probably blindingly obvious, but if anyone has some
> pointers for a novice I would be very grateful.
> 
> If it makes any difference I am using an Altera Stratix.

The LPC2294's external bus is async, so the XCLK is not absolutely needed.
I use a 4X XCLK (use FPGA PLL for this) to register the address and data in
the FPGA.  The address bus will be stable when CS & OE return high, which is
when you latch/register write data or your read data should be stable.

Good luck!!!

Greg Deuerling
Fermi National Accelerator Laboratory