Lpc2000

--- In lpc2000@yahoogroups.com, "Anton Erasmus" <antone@s...> wrote:
>
> On 10 Jan 2006 at 12:33, itsjustimpossible wrote:
> 
> > Hi
> > I need to interface an FPGA to the external bus of the LPC2294 
so that
> > I can directly read and write to the BlockRam internal to the 
FPGA
> > (Arranged as a dual-port RAM).
<snip>
> The external bus is an async bus. When writing use the write 
strobes as the 
> "clock" signal that clocks the data into the specific RAM 
location. 
> Use the external CS signal to qualify the internal CS signal based 
on the address
<snip>

Hi
Thanks to all of you who replied, and thanks for the suggestions. I 
am plugging away at the moment to get a test bench working to 
incorporate them. I did try the quick-stab approach which failed 
miserably so I am now doing it properly.

To answer the last questions, all I need is simple read/write access 
over an 8-bit bus. No multi-master or different bus widths to 
contend with, so I was hoping that it would be straightforward.

It should all make a bit more sense once I have it running in the 
simulator.

cheers
Simon