Lpc2000

> I now have it working and have tried to incorporate as many 
> suggestions as possible. Only problem is it looks a bit too 
> straightforward to be true (safe).

That's always the best solution!

> I am using an XCLK of 60MHz multiplied by 4 in the FPGA and fed to 
> the blockRam.
> An option in the blockRam allows all inputs and outputs to be 
> registered so I have connected its address and data input busses 
> directly to the uP busses. After this it seems the only thing left 
> to do is generate a 'WriteNow' and 'ReadNow' signal to be fed to the 
> BlockRam and to tri-state the data output bus.
> 
> This is all there is...
> 
> 	P_uP_INTERFACE: process (tl_ReadNow, tl_RAM_DATA_OUT)
> 	begin
> 	
> 		if (tl_ReadNow = '1') then
> 			tl_DataIn <= tl_RAM_DATA_OUT;	
> 		else
> 			tl_DataIn <= (others => 'Z');
> 		end if;
> 	
> 	end process P_uP_INTERFACE;

I believe:

tl_DataIn <= (others => 'Z') when (tl_ReadNow = '0')
              else tl_RAM_DATA_OUT;

compiles more efficiently on Altera devices (there is an app
note somewhere for the FLEX devices). Probably makes no difference
on the Stratix devices.

>   tl_WriteNow <= (not tl_CSIn) and (not tl_BLSOIn);
> 
>   tl_ReadNow  <= (not tl_CSIn) and (not tl_OEIn);
> 
> 
> Simulates OK and seems to work in practice. Just seems a bit un-
> complicated.

Just check the setup/hold times. However, since the FPGA is running
off the XCLK, you can tune things pretty nicely.

> Thanks for the help so far, if you have any comments they would be 
> greatly appreciated.

Sounds like you're all set. Let us know how things go.

Dave