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Re: [lpc2000] weird problem in UART

2006-01-17 by Karl Olsen

---- Original Message ----
From: "Mauricio Scaff" <scaffm@...>
To: <lpc2000@yahoogroups.com>
Sent: Tuesday, January 17, 2006 10:25 PM
Subject: [lpc2000] weird problem in UART

> I have the following problem that is very odd.
>
> I have a very simple program that waits one char from the uart0 and
> sends it back to it.
> If I set the baudrate to 57600, it works ok, but if I set the baud
> rate to 115200, the host (PC)  understands any data I send, but the
> LPC just gives Frame errors even if a single byte is sent.....
> I'm using a LPC2146 @ 12Mhz
> Using these constants in the baud rate generator should give an error
> of 0,16%, and the transmission works... Why can't I receive data ?
> Thanks, Mauricio
>
>
> This is the code:
>
> void ser0_init(void)
> {
>  U0IER = 0;
>  U0IIR;
>  U0RBR;
>  U0LSR;
>
>  U0LCR    = 0x83; // Enable access to divisor latchs
>
> // 57600 @ PERCLK = 12Mhz
> //  U0DLL    = 13;
> //  U0DLM    = 0;
> //  U0FDR    = 1<<4|0; // MulVal[7..4]  DivAddVal[3..0]
>
> // 115200 @ PERCLK = 12Mhz
>  U0DLL    = 1;
>  U0DLM    = 0;
>  U0FDR    = 2<<4|11; // MulVal[7..4]  DivAddVal[3..0]
>
>  U0LCR    = 0x03;  // 8n1
>  U0FCR    = 0x87;  // FIFO enabled and cleared; Trigger @ 8 bytes
> }
> [...]

Others have had similar problems with the fractional baudrate generator and
U0DLL=1, search the archive.

Philips has not documented how the fractional baudrate generator actually
works, other than "This pre-scaler takes the VPB clock and generates an
output clock per specified fractional requirements".  When U0DLL=1, this
output clock is equal to the 16xbaud clock that is used when sampling the
RxD signal.

My guess: If that pre-scaler doesn't spread the extra clocks that it inserts
evenly enough, the RxD circuit might not sample the incoming bits correctly,
and you get wrong bytes or framing errors.

philips_apps, are there any limitations of the fractional baudrate generator
at high baudrates?

Karl Olsen

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