Lpc2000

Wow! that's getting really esoteric!

Magnus: Karl is right about the jitter. Even without the delay 
introduced by the timer register being on the peripheral bus, you 
have to take into acount the timer could tick either imediately after 
you load it or any time from then until you load it again. Even if 
the number of instructions and clocks in this is always the same, the 
tick could happen anywhere in the sequence.

By the way, if you use the general approach of a timer interrupt just 
before the ideal time, you have to make it quite a bit before: 
although its called a RISC processor which ideally should have 
one "short" instructions, because of the "load multiple" and "store 
multiple" instructions (e.g. used on function entry/exit), the number 
of clocks per instruction in an ARM can vary a lot (I'm not sure what 
worse case is).

Brendan

--- In lpc2000@yahoogroups.com, "Karl Olsen" <kro@p...> wrote:
>
> --- In lpc2000@yahoogroups.com, "Magnus Lundin" <lundin@m...> wrote:
> > 
> > I'm not shure. This should look as follows in pseudo assembler 
after
> > the timer counter and the D/A adresses are loaded into processor
> > registers:
> >   one load from an on chip register (the counter)
> >   one compare to a fixed short (byte) value
> >   one conditional branch two instructions backwards
> >   [branch not taken]
> >   write to D/A
> > If the loop always runs at least once the the flash preload state
> > should be fixed as the instruction timings. Since there is no 
> > other cache or dynamic memory handling on the lpc2xxx chips
> > this can work if there are no interupts disturbing the instruction
> > flow. Of course this must be tested.
> 
> Loading from the timer register takes at least 8 clocks since it is 
> behind the APB bridge, a compare takes one clock, and a taken 
> backwards jump takes at least 3 clocks, total 12 clocks per loop 
> round.  You then have a jitter of 12 clocks when you terminate the 
> loop.  That is a lot.
> 
> Another way to reduce jitter to ideally zero clocks could be to 
read 
> the timer register once in the timer interrupt handler, and do a 
jump 
> that skips a number of NOPs, depending on how much later than ideal 
> the handler was entered.  Such as:
> 
> # Timer 0 = reset and interrupt at MRx match, so T0TC should now
> # be near zero.  The larger the value, the fewer NOPs should we
> # execute now, and the more NOPs should be skipped.
> #
> # r8 -> T0
> 
> ldr r9, [r8, #8]   /* Load T0TC */
> add pc, pc, r9 lsl #2
> nop
> nop
> nop
> nop
> nop
> ...
> 
> 
> Karl Olsen
>