Lpc2000

Perhaps a combination of IRQ/FIQ can be used?

Let's say FIQs are enabled inside IRQs. Then, one could set TIMER1 
with two match registers: "some time before" (e.g. at 80 µS for 11 
KHz) and "exactly" (at 90.9µS). Then, when the first interrupt is 
caught, make TIMER1 generate FIQs instead of IRQs and enter idle 
mode. Switch to IRQ afterwards. This way one can ensure that the FIQ 
is always served from idle mode. Of course this too uses too much CPU 
resources. A hardware solution is preferable.

Guille

--- In lpc2000@yahoogroups.com, "Rob Jansen" <rob@m...> wrote:
>
> Brendan,
> 
> > I've pointed this out to Philips in the past: hopefully, they'll
> > recognise from this that others have the same issue.
> >
> > None of the work-arounds presented are ideal: a h/w fix is much 
more
> > preferable.
> 
> Just thought of this when I saw "h/w fix" ...
> That is the easy solution, use a sample&hold replaces the variable
> software latencies with a fixed HW one.
> Have an interrupt and a match output generated by the timer. On a 
match
> trigger the S&H and write to the DAC from the interrupt routine.
> This will introduce a delay of 1 sample time but I don't think 
that's a
> big problem in this case.
> 
> A S&H can be easy: one gate of a CD4066 and a capacitor do the 
trick.
> Use the other 3 and some more caps to create a switched capacitor 
filter :o)
> 
> Regards,
> 
>       Rob
>