Lpc2000

--- In lpc2000@yahoogroups.com, "jayasooriah" <jayasooriah@...> wrote:
>
> I was not thinking of this reason when I asked the question.  However,
> after grading, the devices are typically permanantly 'fused' to
> reflect their capabilities.
> 

Actually, that is not really true.  Some CMOS processes have the fuse
link capabilities, but many newer ones do not.  Another grading method
is by "bond out" options, where the packaging process sets the
capabilities available after basic die testing and sorting. That, of
course, cannot be easily reversed by an experimenter. Since Philip's
seems to have FLASH capabilities on the same die as the logic, it
seems logical that they may make use of it for sorting parts with some
minor defects.  If that is what they are doing, then the deleted
functions may work fine under nominal temperature/voltage/frequency
conditions, but will fail at one of the "corner" conditions.  


TANSTAAFL - Robert A. Heinlein

-- Dave