Lpc2000

Hello Jaya,

On Monday 06 February 2006 02:13, Jayasooriah wrote:
> Hi Tom,
>
> If we accept what you say, it appears trading one instruction cycle off the
> window of opportunity for exception handling is a silly thing to do.
>
> The designers made a deliberate tradeoff.  I am asking why.  Does this
> action dismiss the threat or does it just reduce the window of opportunity?
>
> One can only draw inferences from Philips silence that the latter is the
> case.

Sure - my bet is that they had a nice weekend, and didn't bother checking that 
forum.

>
> Kind regards,
>
> Jaya
>
> PS1:  I am curious as to where it is stated that JTAG cannot run above the
> rate the CPU is running at.

http://www.arm.com/support/faqip/3732.html
The LPCs are ARM7TDMI-S cores, requiring the synchronization logic shown in 
the above faq entry. That means they can't run TCK above 1/6th of the core 
frequency.

>
> PS2:  In counting instruction cycles, you have to take into account
> pipeline delays.

Regards,

Dominic