Lpc2000

-snip--
> 
> Hello there,
> 
> It is certainly more reaasuring to see Philips' presence here.
> I wonder if you would be able to describe more concisely when the code
> protection
> feature of LPC2000 is/will be introduced, and in just a few words
what it
> entails.
> Hugh at Ashling has recently covered this, but this issue seemed to need
> confirmation.
> Are you able to alleviate any doubts/hesitations ?
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The protection (disabling JTAG) happens first thing at power up no
matter if protection is enabled or not. 
Then the bootloader checks whether the protection is supposed to be
enabled and enables the JTAG interface if the protection pattern is
not found in the corresponding memory location. 

This is a preliminary wording of future documentation:

Code Read Protection
--------------------
Code read protection is enabled by programming the flash address
location 0x1FC (User flash sector 0) with value 0x87654321 (2271560481
Decimal). Address 0x1FC is used to allow some room for the fiq
exception handler. When the code read protection is enabled the JTAG
debug port, external memory boot and the following ISP commands are
disabled.

Read Memory
Write to RAM
Go
Copy RAM to Flash
Write Port to RAM

The ISP commands mentioned above terminates with return code
CODE_READ_PROTECTION_ENABLED.
The ISP erase command only allows erasure of all user sectors (not
just one) when the code read protection is enabled. This limitation
does not exist if the code read protection is not enabled. IAP
commands are not affected by the code read protection.

Hope this helps.
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> 
> Also, I am led to believe that die size / economy will restrict
LPC2000 for
> quite some
> time to 16 K SRAM. Correct ?
> Will we ever see > 16 K again ?
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Yes you will see more than 16k (32k to begin with) late fall this year. 

Best regards, Robert